CY7C144 Cypress Semiconductor Corporation., CY7C144 Datasheet
CY7C144
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CY7C144 Summary of contents
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... CY7C144/5 to handle situations when mul- tiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be utilized as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM ...
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... TQFP Top View CY7C144 CY7C145 CY7C144 INT BUSY L GND 52 51 M/S BUSY ...
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... L cleared when left port reads location 1FFE. INT location 1FFF and is cleared when right port reads location 1FFF. Busy Flag Master or Slave Select Power Ground 3 CY7C145 CY7C144 BUSY ...
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... CC Ind V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX (except output enable means no address or control lines change. This applies only to inputs at CMOS 4 CY7C145 CY7C144 7C144-35 7C144-55 7C145-35 7C145- 160 160 30 30 Ambient Temperature + ...
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... Com’ > V – 0.2V Ind V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX Test Conditions MHz 5. CY7C145 CY7C144 7C144-35 7C144-55 7C145-35 7C145-55 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0 + +10 10 ...
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... HZCE LZCE 6 CY7C145 CY7C144 5V R1=893 OUTPUT R2=347 =1.4V (c) Three-State Delay (Load 3) C144 C144-9 7C144-35 7C144-55 7C145-35 7C145-55 Min. Max. Min. Max ...
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... CY7C145 CY7C144 7C144-55 7C145-55 Max. Min. Max. Unit ...
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... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L 19. BUSY = HIGH for the writing port. 20 LOW [15, 16 [15, 17, 18] t ACE t DOE DATA VALID [19, 20 MATCH t PWE t SD VALID MATCH t WDD 8 CY7C145 CY7C144 DATA VALID C144-10 t HZCE t HZOE t PD C144- DDD VALID C144-12 ...
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... AW t PWE t SD DATAVALID t HZWE HIGH IMPEDANCE PWE . HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply SD . PWE 9 CY7C145 CY7C144 LZOE C144- LZWE C144- allow the I/O drivers to turn off and ...
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... SPS [25 VALID ADDRESS SOP t SD DATA VALID SWRD t SOP READ CYCLE MATCH t SPS MATCH = CE = HIGH CY7C145 CY7C144 t OHA t ACE DATA VALID OUT t DOE C144-15 C144-16 ...
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... Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATAIN ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY t WC MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C145 CY7C144 BHA t BDD t DDD VALID C144–17 C144–18 ...
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... BUSY will be asserted PS [29] ADDRESS MATCH BLC ADDRESS MATCH BLC [29 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 12 CY7C145 CY7C144 t BHC C144-19 t BHC C144-20 C144-21 C144-22 ...
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... depends on which enable pin (CE INS INR t WC WRITE 1FFF [30 [31] [31] t INR t WC WRITE 1FFE [30 [31] [31] t INR ) is deasserted first R asserted last CY7C145 CY7C144 C144- READ 1FFF C144-24 C144- READ 1FFE C144-26 ...
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... Architecture The CY7C144/5 consists array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit indepen- dent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication ...
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... X I/O Left I/O Right 0-7/8 0-7 CY7C145 CY7C144 Right Port INT R 1FFE 1FFF Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change ...
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... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4.5V CC 5.0 T =25° 200 400 600 800 1000 CAPACITANCE (pF) 16 CY7C145 CY7C144 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 V =5. =25° 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 ...
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... Ordering Information 8K x8 Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C144-15AC CY7C144-15JC 25 CY7C144-25AC CY7C144-25JC CY7C144-25AI CY7C144-25JI 35 CY7C144-35AC CY7C144-35JC CY7C144-35AI CY7C144-35JI 55 CY7C144-55AC CY7C144-55JC CY7C144-55AI CY7C144-55JI 8K x9 Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C145-15AC CY7C145-15JC 25 CY7C145-25AC CY7C145-25JC CY7C145-25AI CY7C145-25JI 35 CY7C145-35AC CY7C145-35JC CY7C145-35AI CY7C145-35JI 55 CY7C145-55AC ...
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... Package Diagrams 64-Pin Thin Plastic Quad Flat Pack A65 80-Pin Thin Plastic Quad Flat Pack A80 18 CY7C145 CY7C144 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 68-Lead Plastic Leaded ChipCarrierJ81 CY7C145 CY7C144 ...