HD6417709 Renesas Electronics Corporation., HD6417709 Datasheet
HD6417709
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HD6417709 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Hitachi SuperH™ RISC engine ADE-602-250 Rev. 1.0 09/21/01 Hitachi, Ltd. SH7709S Hardware Manual ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions necessary for configuring a user system. This LSI is built in with a variety of peripheral functions such as cache memory, memory management unit ...
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User manuals for development tools Name of Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual Simulator/Debugger User’s Manual Hitachi Embedded Workshop User’s Manual Application note Name of Document C/C++ Compiler Guide Document No. ADE-702-246 ADE-702-186 ADE-702-201 Document No. ADE-xxx-xxx ...
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Section 1 Overview and Pin Functions 1.1 SH7709S Features .............................................................................................................. 1.2 Block Diagram.................................................................................................................... 1.3 Pin Description ................................................................................................................... 1.3.1 Pin Assignment ..................................................................................................... 1.3.2 Pin Function .......................................................................................................... Section 2 CPU ...................................................................................................................... 19 2.1 Register Configuration ....................................................................................................... 19 2.1.1 Privileged Mode and Banks ...
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MMU Functions ................................................................................................................. 73 3.4.1 MMU Hardware Management .............................................................................. 73 3.4.2 MMU Software Management................................................................................ 73 3.4.3 MMU Instruction (LDTLB).................................................................................. 74 3.4.4 Avoiding Synonym Problems ............................................................................... 76 3.5 MMU Exceptions ............................................................................................................... 78 3.5.1 TLB Miss Exception ............................................................................................. 78 3.5.2 TLB ...
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Register Configuration .......................................................................................... 109 5.2 Register Description ........................................................................................................... 109 5.2.1 Cache Control Register (CCR).............................................................................. 109 5.2.2 Cache Control Register 2 (CCR2) ........................................................................ 110 5.3 Cache Operation ................................................................................................................. 113 5.3.1 Searching the Cache.............................................................................................. 113 5.3.2 Read Access .......................................................................................................... 115 5.3.3 ...
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Section 7 User Break Controller 7.1 Overview ............................................................................................................................ 153 7.1.1 Features ................................................................................................................. 153 7.1.2 Block Diagram ...................................................................................................... 154 7.1.3 Register Configuration .......................................................................................... 155 7.2 Register Descriptions.......................................................................................................... 156 7.2.1 Break Address Register A (BARA) ...................................................................... 156 7.2.2 Break Address Mask Register ...
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Canceling Standby Mode ...................................................................................... 193 8.4.3 Clock Pause Function............................................................................................ 194 8.5 Module Standby Function .................................................................................................. 195 8.5.1 Transition to Module Standby Function................................................................ 195 8.5.2 Clearing Module Standby Function ...................................................................... 195 8.6 Timing of STATUS Pin Changes....................................................................................... 196 8.6.1 Timing ...
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Features ................................................................................................................. 227 10.1.2 Block Diagram ...................................................................................................... 229 10.1.3 Pin Configuration .................................................................................................. 230 10.1.4 Register Configuration .......................................................................................... 232 10.1.5 Area Overview ...................................................................................................... 233 10.1.6 PCMCIA Support.................................................................................................. 236 10.2 BSC Registers .................................................................................................................... 239 10.2.1 Bus Control Register 1 (BCR1) ............................................................................ ...
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Pin Configuration .................................................................................................. 334 11.1.4 Register Configuration .......................................................................................... 335 11.2 Register Descriptions.......................................................................................................... 337 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 337 11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 338 11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......................... ...
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Input Capture Function.......................................................................................... 407 12.4 Interrupts ............................................................................................................................ 408 12.4.1 Status Flag Setting Timing.................................................................................... 408 12.4.2 Status Flag Clearing Timing ................................................................................. 409 12.4.3 Interrupt Sources and Priorities............................................................................. 409 12.5 Usage Notes........................................................................................................................ 410 12.5.1 Writing to Registers .............................................................................................. 410 12.5.2 Reading ...
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Overview ............................................................................................................................ 431 14.1.1 Features ................................................................................................................. 431 14.1.2 Block Diagram ...................................................................................................... 432 14.1.3 Pin Configuration .................................................................................................. 435 14.1.4 Register Configuration .......................................................................................... 436 14.2 Register Descriptions.......................................................................................................... 436 14.2.1 Receive Shift Register (SCRSR)........................................................................... 436 14.2.2 Receive Data Register (SCRDR) .......................................................................... 437 ...
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Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview ............................................................................................................................ 515 16.1.1 Features ................................................................................................................. 515 16.1.2 Block Diagram ...................................................................................................... 516 16.1.3 Pin Configuration .................................................................................................. 519 16.1.4 Register Configuration .......................................................................................... 520 16.2 Register Descriptions.......................................................................................................... 521 16.2.1 Receive Shift Register (SCRSR)........................................................................... ...
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Port D Control Register (PDCR) .......................................................................... 577 18.3.5 Port E Control Register (PECR)............................................................................ 578 18.3.6 Port F Control Register (PFCR)............................................................................ 579 18.3.7 Port G Control Register (PGCR) .......................................................................... 580 18.3.8 Port H Control Register (PHCR)........................................................................... 581 18.3.9 Port J ...
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Register Description.............................................................................................. 611 19.12.2 Port L Data Register (PLDR)................................................................................ 612 19.13 SC Port................................................................................................................................ 613 19.13.1 Register Description.............................................................................................. 613 19.13.2 Port SC Data Register (SCPDR) ........................................................................... 614 Section 20 A/D Converter 20.1 Overview ............................................................................................................................ 617 20.1.1 Features ................................................................................................................. 617 20.1.2 ...
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Hitachi User Debugging Interface (H-UDI)....................................................................... 645 22.2.1 Pin Descriptions .................................................................................................... 645 22.2.2 Block Diagram ...................................................................................................... 646 22.3 Register Descriptions.......................................................................................................... 646 22.3.1 Bypass Register (SDBPR) .................................................................................... 647 22.3.2 Instruction Register (SDIR) .................................................................................. 647 22.3.3 Boundary Scan Register (SDBSR)........................................................................ 648 22.4 ...
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Appendix B Memory-Mapped Control Registers B.1 Register Address Map ........................................................................................................ 747 B.2 Register Bits ....................................................................................................................... 753 Appendix C Product Lineup Appendix D Package Dimensions xiv ...................................................... 747 ............................................................................................. 765 ................................................................................... 766 ...
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Section 1 Overview and Pin Functions 1.1 SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Hitachi-original RISC-type TM SuperH * architecture CPU as its core that has an on-chip multiplier, cache memory, and a memory management ...
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Table 1.1 SH7709S Features Item Features CPU Original Hitachi SuperH architecture Object code level compatible with SH-1, SH-2 and SH-3 (SH7708) 32-bit internal data bus General-register files Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers Four ...
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Table 1.1 SH7709S Features (cont) Item Features Cache memory 16-kbyte cache, mixed instruction/data 256 entries, 4-way set associative, 16-byte block length Write-back, write-through, LRU replacement algorithm 1-stage write-back buffer Maximum 2 ways of the cache can be locked Interrupt 23 ...
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... Abbr. SH7709S 3.3 4 Power Supply Voltage Operating I/O Internal Frequency ± ± 0.3V 2.0 0.15V* 200MHz ± 1.9 0.15V 167MHz + 1.8 0.25V 133MHz – 1.8 0.15V Model Name Packege HD6417709SHF200 208-pin plastic HQFP (FP-208E) HD6417709SF167 208-pin plastic LQFP (FP-208C) HD6417709SBP167 240-pin CSP V (BP-240A) HD6417709SF133 208-pin plastic LQFP (FP-208C) ...
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... Internal frequency: maximum 200 MHz(200 MHz model), 167 MHz (167 MHz model) 133.34 MHz (133 MHz model), 100 MHz (100 MHz model); external frequency: maximum 66.67 MHz 0.25-µm CMOS/5-layer metal Model Name Packege HD6417709SBP133 240-pin CSP V (BP-240A) HD6417709SF100 208-pin plastic LQFP (FP-208C) HD6417709SBP100 240-pin CSP V (BP-240A) 5 ...
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Block Diagram MMU TLB CCN CACHE BRIDGE ASERAM UDI INTC CPG/WDT External bus interface Legend: ADC: A/D converter ASERAM: ASE memory AUD: Advanced user debugger BSC: Bus state controller CACHE: Cache memory CCN: Cache memory controller CMT: Compare match ...
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Pin Description 1.3.1 Pin Assignment STATUS0/PTJ[6] 157 STATUS1/PTJ[7] 158 TCLK/PTH[7] 159 IRQOUT 160 V Q 161 SS CKIO 162 V Q 163 CC TxD0/SCPT[0] 164 SCK0/SCPT[1] 165 TxD1/SCPT[2] 166 SCK1/SCPT[3] 167 TxD2/SCPT[4] 168 SCK2/SCPT[5] 169 RTS2/SCPT[6] 170 RxD0/SCPT[0] 171 ...
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Note: The pin area enclosed in broken lines is an inner ...
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Pin Function Table 1.3 SH7709S Pin Function Number of Pins FP-208C BP-240A Pin Name FP-208E 1 D2 MD1 2 C2 MD2 3 E2 Vcc-RTC 4 D1 XTAL2 5 D3 EXTAL2 6 E1 Vss-RTC 7 C3 NMI 8 E3 IRQ0/IRL0/PTH[0] ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E 26 K2 D20/PTA[ Vss — K4 Vss 28 K1 D19/PTA[ Vcc — L4 Vcc 30 L2 D18/PTA[ D17/PTA[ ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E VssQ VccQ ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E 82 V11 A23 83 W11 VssQ 84 T12 A24 85 U12 VccQ 86 V12 A25 BS/PTK[4] 87 W12 RD 88 T13 WE0/DQMLL 89 U13 WE1/DQMLU/WE 90 ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E CE2A/PTE[4] 103 V17 CE2B/PTE[5] 104 V16 105 T18 CKE/PTK[5] RAS3L/PTJ[0] 106 U18 107 U19 PTJ[1] CASL/PTJ[2] 108 R18 109 T19 VssQ CASU/PTJ[3] 110 T17 111 R19 ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E WAIT 123 M19 RESETM 124 M18 ADTRG/PTH[5] 125 M17 IOIS16/PTG[7] 126 M16 ASEMD0/PTG[6] 127 L19 ASEBRKAK/PTG[5] 128 L18 129 L16 PTG[4]/CK102 130 L17 AUDATA[3]/PTG[3] 131 K18 ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E 144 G19 MD0 145 F16 Vcc-PLL1 146 F17 CAP1 147 F18 Vss-PLL1 148 F19 Vss-PLL2 149 E16 CAP2 150 E17 Vcc-PLL2 151 D16 AUDCK/PTH[6] 152 E19 ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E 168 C14 TxD2/SCPT[4] 169 D14 SCK2/SCPT[5] RTS2/SCPT[6] 170 A13 171 B13 RxD0/SCPT[0] 172 C13 RxD1/SCPT[2] 173 D13 Vss — A12 Vss 174 B12 RxD2/SCPT[4] 175 C12 ...
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Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name FP-208E MCS[0]/PTC[0]/PINT[0] 188 D8 189 C8 DRAK0/PTD[1] 190 B8 DRAK1/PTD[0] DREQ0/PTD[4] 191 A8 DREQ1/PTD[6] 192 D7 RESETP 193 C7 194 B7 CA 195 A7 MD3 196 D6 ...
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When this LSI is used on the user system alone, without an emulator and the H-UDI, hold this pin at high level. *6 B2, B1, C1, U1, V1, W1, V2, W2, W3, W17, W18, W19, V18, V19, B19, A19, ...
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Register Configuration 2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7709S normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. ...
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Notes functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. Banked register *2 Figure 2.1 User Mode Register Configuration BANK0 BANK0* 2 ...
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R0_BANK1* 2 R1_BANK1* 2 R2_BANK1* 2 R3_BANK1* 2 R4_BANK1* 2 R5_BANK1* 2 R6_BANK1* 2 R7_BANK1 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC , ...
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Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type General registers Control registers System registers Note: Register values are initialized at power-on reset or manual reset. 2.1.2 General Registers There are 16 general ...
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System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the ...
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SSR 31 SPC 31 GBR 31 VBR 0–––––––––––––––––––––0 MD: Processor operation mode bit: Indicates the processor operation mode as follows: MD =1: Privileged mode User mode MD ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded ...
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Instruction Features 2.3.1 Execution Environment Data Length: The SH7709S instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can ...
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T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Register direct Rn Effective address is register Rn. (Operand is ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method Register @(disp:4, Effective address is register Rn contents with indirect with Rn) 4-bit displacement disp added. After disp is displacement zero-extended multiplied ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method PC-relative @(disp:8, Effective address is register PC contents with with PC) 8-bit displacement disp added. After disp is displacement zero-extended multiplied by ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method PC-relative Rn Effective address is sum of register PC and Rn contents. Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR ...
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Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register ...
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Table 2.3 Instruction Formats (cont) Instruction Format 15 nm format xxxx nnnn mmmm 15 md format xxxx xxxx mmmm 15 nd4 format xxxx xxxx Source Operand 0 mmmm: register direct xxxx mmmm: register indirect mmmm: register indirect with post- increment ...
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Table 2.3 Instruction Formats (cont) Instruction Format nmd 15 format xxxx nnnn mmmm d format 15 xxxx xxxx 15 d12 format xxxx dddd nd8 format 15 xxxx nnnn 15 i format xxxx xxxx ni format 15 xxxx nnnn Note: In ...
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Instruction Set 2.4.1 Instruction Set Classified by Function The SH7709S instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT ...
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Table 2.4 Classification of Instructions (cont) Operation Classification Types Code Arithmetic 21 MUL operations (cont) MULS MULU NEG NEGC SUB SUBC SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL ...
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Table 2.4 Classification of Instructions (cont) Operation Classification Types Code Branch BRA BRAF BSR BSRF JMP JSR RTS System 15 CLRMAC control CLRT CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: ...
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Table 2.5 lists the SH7709S instruction code formats. Table 2.5 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST mnemonic Instruction MSB LSB code Operation , summary (xx) M/Q/T & <<n, >>n Privileged mode Execution cycles T bit ...
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Table 2.6 lists the SH7709S data transfer instructions Table 2.6 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn (disp MOV.W @(disp,PC),Rn extension (disp MOV.L @(disp,PC),Rn Rm MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn Rm MOV.L Rm,@Rn (Rm) MOV.B @Rm,Rn ...
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Table 2.6 Data Transfer Instructions (cont) Instruction Operation Rm MOV.W Rm,@(R0,Rn) Rm MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn extension (R0 + Rm) MOV.W @(R0,Rm),Rn extension (R0 + Rm) MOV.L @(R0,Rm),Rn R0,@(disp,GBR) R0 MOV.B R0,@(disp,GBR) R0 MOV.W R0,@(disp,GBR) R0 MOV.L ...
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Table 2.7 lists the SH7709S arithmetic instructions. Table 2.7 Arithmetic Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry ADDV Rm,Rn Overflow If R0 imm, ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation Signed operation of DMULS.L Rm, MACL 32 Unsigned operation of DMULU.L Rm, MACL 32 Rn – else 0 A byte ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation 0–Rm NEG Rm,Rn 0–Rm–T NEGC Rm,Rn Borrow Rn–Rm SUB Rm,Rn Rn–Rm–T SUBC Rm,Rn Borrow Rn–Rm SUBV Rm,Rn Underflow Note: The normal number of execution cycles is shown. The value in parentheses is the ...
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Table 2.8 lists the SH7709S logic operation instructions. Table 2.8 Logic Operation Instructions Instruction Operation Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & imm AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm NOT Rm, ...
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Table 2.9 lists the SH7709S shift instructions. Table 2.9 Shift Instructions Instruction Operation T Rn ROTL Rn LSB ROTR ROTCL ROTCR << Rm SHAD Rm,Rn Rn < >> ...
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Table 2.10 lists the SH7709S branch instructions. Table 2.10 Branch Instructions Instruction Operation disp BF label nop Delayed branch BF/S label disp nop ...
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Table 2.11 lists the SH7709S system control instructions. Table 2.11 System Control Instructions Instruction Operation 0 MACH, MACL CLRMAC 0 S CLRS 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm SSR LDC ...
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Table 2.11 System Control Instructions (cont) Instruction Operation (Rm) LDC.L @Rm R4_BANK (Rm) LDC.L @Rm R5_BANK (Rm) LDC.L @Rm R6_BANK (Rm) LDC.L @Rm R7_BANK Rm MACH LDS Rm,MACH ...
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Table 2.11 System Control Instructions (cont) Instruction Operation R4_BANK STC R4_BANK,Rn R5_BANK STC R5_BANK,Rn R6_BANK STC R6_BANK,Rn R7_BANK STC R7_BANK,Rn Rn–4 STC.L SR,@–Rn Rn–4 STC.L GBR,@–Rn Rn–4 STC.L VBR,@–Rn Rn–4 STC.L SSR,@–Rn Rn–4 STC.L SPC,@–Rn Rn–4 STC.L R0_BANK, @–Rn Rn–4 ...
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Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: • When there is contention between an instruction fetch and data access • When ...
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Instruction Code Map Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map Instruction Code Fx: 0000 MD: 00 MSB LSB 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC SR,Rn 0000 Rn ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 0100 Rn Fx 0000 SHLL Rn 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L MACH,@-Rn 0100 Rn 00MD 0011 STC.L SR,@-Rn 0100 Rn ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 11MD imm/disp 1001 Rn disp MOV.W @(DISP:8,PC),RN 1010 ...
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Processor States and Processor Modes 2.5.1 Processor States The SH7709S has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters ...
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From any state when RESETP = 0 Power-on reset Interrupt Bus-released state Bus Bus request request clearance Sleep mode CA = 1,RESETP=0 Note: * The hardware standby mode is entered when the CA pin goes low from any state. Figure ...
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56 ...
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7709S has an on-chip memory management unit (MMU) that implements address translation. The SH7709S features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables ...
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MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by ...
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Process 1 Physical memory Process 1 Process 1 Process 2 Process 3 Figure 3.1 MMU Functions Virtual memory Process 1 Physical memory (1) Virtual Process 1 memory Physical memory Process 2 Process 3 (3) MMU Physical memory (2) MMU Physical ...
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SH7709S MMU Virtual Address Space (1) P0, P3, and U0 Areas For the P0, P3, and U0 areas, access through the cache and address translation using the TLB are possible. These areas can be mapped to any external memory ...
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External memory space Area 0 Area 1 Area 2 Area 3 Area 4 Area P0 Area 5 Area 6 Area 7 Area P1 Area P2 Area P3 Area P4 Privileged mode Figure 3.2 Virtual Address Space (MMUCR.AT=1) Area U0 Address ...
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Physical Address Space: (1) P0, P3, and U0 Areas The P0, P3, and U0 areas can be accessed through the cache. When CCR. these areas will be accessed through the cache. The caching mode, copy-back or write-through, is ...
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H'0000 0000 Area P0 H'8000 0000 Area P1 H'A000 0000 Area P2 H'C000 0000 Area P3 H'E000 0000 Area P4 H'FFFF FFFF Privileged mode Figure 3.3 Physical Address Space (MMUCR.AT=0) Single Address Translation: When the MMU is enabled, the virtual ...
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If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and ...
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Register Configuration A register that has an undefined initial value must be initialized by software. Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration Name Page table entry register high Page table entry register ...
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The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the virtual address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. 5. The MMU control register (MMUCR) ...
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TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for ...
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VPN (31–17) VPN (11–10) ASID Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN ...
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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits and ASID bits PTEH are used as the index number regardless of the ...
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Virtual address Index 0 VPN(31–17) VPN(11–10) 31 Address array 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual ...
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The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH 0) but not when there is sharing (SH 1). When single virtual ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., ...
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MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the ...
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MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR ...
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MMUCR Index PTEH register VPN VPN Write VPN(31–17) VPN(11–10 Address array Figure 3.10 Operation of LDTLB Instruction 0 Way selection PTEL register ...
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Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded ...
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When using a 4-kbyte page Virtual address VPN Physical address PPN When using a 1-kbyte page Virtual address 31 11 VPN Physical address 31 11 PPN Figure 3.11 Synonym Problem 0 Offset ...
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MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry ...
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If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return ...
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TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid ...
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Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is ...
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No VPNs match? TLB miss exception PR check 00/01 W R/W? TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.12 MMU Exception Generation Flowchart 82 Start and (MMUCR. ...
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Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.13 shows the MMU exception signals in the instruction fetch mode. : Exception source stage IF = Instruction fetch ID = Instruction decode EX = ...
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Figure 3.14 shows the MMU exception signals in the data access mode Exception source stage : Stage cancellation for instruction that has begun execution IF = Instruction fetch ID = Instruction decode EX ...
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The following 2 types of operations on the address array are possible. (1) Address Array Read Reads VPN, V bit, and ASID from the entry that corresponds to the entry address and way that were specified in the address field. ...
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TLB Address Array Access Read access 31 Address field 11110010 31 Data field Write access 31 Address field 11110010 31 Data field VPN (2) TLB Data Array Access Read/write access 31 Address field 11110011 ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN ...
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88 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the ...
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PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The contents of PC and SR ...
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Table 4.2 Exception Event Vectors Exception Current Type Instruction Exception Event Reset Aborted Power-on Manual reset H-UDI reset General Aborted CPU address error exception and retried (instruction access) events TLB miss TLB invalid (instruction access) TLB protection violation (instruction access) ...
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Table 4.2 Exception Event Vectors (cont) Exception Current Type Instruction Exception Event General Completed User breakpoint trap 2 exception events DMA address error General Completed Nonmaskable interrupt interrupt requests External hardware interrupt H-UDI interrupt Notes: *1 Priorities are indicated from ...
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Pipeline Sequence: Instruction n Instruction Instruction Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and RIE (instruction simultaneous detection Handling Order: TLB miss (instruction n) Re-execution of instruction ...
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Exception Codes Table 4.3 lists the exception codes written to bits 11–0 of the ...
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Table 4.3 Exception Codes (cont) Exception Type General interrupt requests (cont) Note: Exception codes H'120, H'140, and H'3E0 are reserved. 4.2.5 Exception Request Masks When the BL bit exceptions and interrupts are accepted general ...
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Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) ...
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Exception Handling Operation 4.4.1 Reset The reset sequence is used to power up or restart the SH7709S from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, ...
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General Exceptions When the SH7709S encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of PC and SR are saved to SPC and SSR, respectively. 2. The BL bit ...
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H-UDI Reset Conditions: H-UDI reset command input (see section 22.4.3, H-UDI Reset) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits ...
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TLB invalid exception Conditions: Comparison of TLB addresses shows address match but Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in ...
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CPU address error Conditions: a. Instruction fetch from odd address ( Word data accessed from addresses other than word boundaries ( Longword accessed from addresses other than longword ...
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User break point trap Conditions: When a break condition set in the user break controller is satisfied Operations: When a post-execution break occurs the instruction immediately after the instruction that set the break point is set in SPC. ...
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IRQ Pin Interrupts Conditions: The IRQ pin is asserted, SR.IMASK is lower than the IRQ priority level, and the BL bit The interrupt is accepted at an instruction boundary. Operations: The PC value after the ...
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Cautions Return from exception handling Check the BL bit in SR with software. When SPC and SSR have been saved to external memory, set the BL bit before restoring them. Issue an RTE instruction, which ...
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When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This will be identified ...
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106 ...
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Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instruction/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number ...
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Address array (ways 0–3) Entry Tag address Entry Entry 255 22) bits Address Array: The V bit indicates whether the entry data is valid. When ...
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The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU and Way Replacement (When the cache lock function is not used) LRU (5–0) 000000, 000100, 010100, 100000, 110000, ...
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Reserved bits. Always 0 when reading. Data written here is also always 0. CF: Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads ...
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W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR the prefetched data will always be loaded into Way2. In all other conditions the prefetched data ...
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Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Cache Miss DSP bit W3LOAD W3LOCK don't care Do ...
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Cache Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates ...
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Virtual address Entry selection Tag address MMU 1 255 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 ...
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Read Access Read Hit read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry ...
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PA (31–4) PA (31–4): Longword 0–3: Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is ...
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Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address and way that were specified in the address field. No associative operation will be performed, regardless of the value of the ...
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Data Array Write Writes the longword data set in the data field into the entry that corresponds to the entry address and way that were specified in the address field. The longword data will be written to the entry ...
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Examples of Usage (1) Invalidating a Specific Entry A specific cache entry can be invalidated by writing the entry's U and V bits. When the A bit is 1, the tag address specified by the write ...
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120 ...
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process ...
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Block Diagram Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRL3–IRL0 4 IRLS3–IRLS0 IRQ0–IRQ5 6 PINT0–PINT15 16 (Interrupt request) DMAC (Interrupt request) IrDA (Interrupt request) SCIF (Interrupt request) SCI (Interrupt request) ADC (Interrupt request) TMU (Interrupt ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 INTC Pins Name Nonmaskable interrupt input pin Interrupt input pins Port interrupt input pins Bus request output pin Abbreviation I/O Description NMI I Input of interrupt request signal, ...
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Register Configuration The INTC has the 12 registers listed in table 6.2. Table 6.2 INTC Registers Name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 PINT interrupt enable register Interrupt priority register A Interrupt priority ...
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Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL,PINT, and on-chip peripheral modules. Each interrupt has a priority level (0–16), with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 6.2.1 NMI ...
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Interrupts IRQ4–IRQ0 can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of I3–I0 in the SR register (but only when the RTC 32-kHz oscillator is used). 6.2.3 IRL Interrupts IRL ...
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IRL3–IRL0/IRLS3–IRLS0 Pins and Interrupt Levels Table 6.3 IRL3/ IRL2/ IRL1/ IRLS3 IRLS2 IRLS1 ...
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PINT Interrupts PINT interrupts are input by level from pins PINT0–PINT15. The priority level can be set by interrupt priority register D (IPRD range from 0 to 15, in groups of PINT0–PINT7 and PINT8–PINT15. The PINT0/1 interrupt ...
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Interrupt Exception Handling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the ...
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Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) INTEVT Code Interrupt Source (INTEVT2 Code) NMI H'1C0 (H'1C0) H-UDI H'5E0 (H'5E0) IRQ IRQ0 H'200–3C0* (H'600) IRQ1 H'200–3C0* (H'620) IRQ2 H'200–3C0* (H'640) IRQ3 H'200–3C0* (H'660) IRQ4 H'200–3C0* (H'680) IRQ5 H'200–3C0* ...
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Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) (cont) INTEVT Code Interrupt Source (INTEVT2 Code) RTC ATI H'480 (H'480) PRI H'4A0 (H'4A0) CUI H'4C0 (H'4C0) SCI0 ERI H'4E0 (H'4E0) RXI H'500 (H'500) TXI H'520 (H'520) TEI H'540 (H'540) ...
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Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) INTEVT Code Interrupt Source (INTEVT2 Code) NMI H'1C0 (H'1C0) H-UDI H'5E0 (H'5E0) IRL(3: IRL = 0000 H'200 (H'200) IRL(3: 0001 H'220 (H'220 IRL(3:0) = ...
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Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) (cont) INTEVT Code Interrupt Source (INTEVT2 Code) SCIF ERI2 H'200–3C0* RXI2 H'200–3C0* BRI2 H'200–3C0* TXI2 H'200–3C0* ADC ADI H'200–3C0* TMU0 TUNI0 H'400 (H'400) TMU1 TUNI1 H'420 (H'420) TMU2 TUNI2 H'440 ...
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Table 6.6 Interrupt Levels and INTEVT Codes Interrupt level 134 INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 ...
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INTC Registers 6.3.1 Interrupt Priority Registers (IPRA–IPRE) Interrupt priority registers (IPRA to IPRE) are 16-bit readable/writable registers in which priority levels from are set for on-chip peripheral module, IRQ, and ...
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Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or ...
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Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a ...
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Bit 12—IRLS Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the IRQLVL bit is 1. Bit 12: IRLSEN Description Pins IRLS3–IRLS0 disabled 0 Pins IRLS3–IRLS0 enabled 1 Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether ...
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Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge the low level. Bit 5: IRQ21S Bit 4: IRQ20S 0 0 ...
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Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is ...
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PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is ...
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Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H' power-on reset or manual reset, but ...
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Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R Description 0 No ...
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Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H' power-on reset or manual reset, but is not initialized ...
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Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request has been generated. B Description it 3: DEI3R 0 DEI3 interrupt request not generated 1 DEI3 interrupt request generated Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 ...
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Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has been generated. B Description it 4: ADIR 0 ADI ...
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INTC Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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No ICR1.BLMSK = 1? Yes NMI? No Yes Yes IRQOUT = low Set interrupt cause in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bits Branch to exception handler I3–I0: Interrupt mask ...
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Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used ...
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Table 6.8 Interrupt Response Time Item NMI Time for priority 0.5 Icyc decision and SR + 0.5 mask bit comparison + 0.5 Wait time until end sequence being executed by CPU Time from interrupt 5 Icyc ...
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Table 6.8 Interrupt Response Time (cont) Item NMI Response Total (5 time Icyc + 0.5 + 0.5 Minimum 7.5 2 case* Maximum 8 case* Icyc: Duration of one cycle of internal clock supplied to CPU. ...
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Icyc + 0 Pcyc IRL Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: Instruction decode: Fetched instruction ...
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Section 7 User Break Controller 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. ...
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Block Diagram Figure 7.1 shows a block diagram of the UBC. Access IAB Control LDB/IDB/ XDB/YDB Legend BBRA: Break bus cycle register A BARA: Break address register A BAMRA: Break address mask register A BASRA: Break ASID register A ...
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Register Configuration Table 7.1 Register Configuration Name Abbr. Break address register A BARA Break address mask BAMRA R/W register A Break bus cycle register A BBRA Break address register B BARB Break address mask BAMRB R/W register B Break ...
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Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000. Bit: 31 BAA31 Initial value: 0 ...
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Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. A power-on reset initializes BAMRA to H'00000000. Bit: 31 BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 ...
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Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size ...
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Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 Bit 2: RWA0 Bits 1 and ...
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Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. A power-on reset initializes BARB to H'00000000. Bit: 31 BAB31 Initial value: 0 R/W: R/W Bit: ...
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Break Address Mask Register B (BAMRB) BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. A power-on reset initializes BAMRB to H'00000000. Bit: 31 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 ...
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Break Data Register B (BDRB) BDRB is a 32-bit read/write register. A power-on reset initializes BDRB to H'00000000. Bit: 31 BDB31 Initial value: 0 R/W: R/W Bit: 23 BDB23 Initial value: 0 R/W: R/W Bit: 15 BDB15 Initial value: ...
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Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000. Bit: 31 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 ...
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Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the ...
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Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 Bit 2: RWB0 Bits 1 and ...
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Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition break is set before or after instruction execution break ...
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Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description 0 All BASRA bits are included in break condition, ASID ...
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Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, ...
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Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB Description 0 PC break of channel B is set before instruction execution 1 ...
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Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 reset initializes BETR to H'0000. When a ...
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Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR ...
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Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: PID Description Even PID indicates ...
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Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set reading BRDR. Bit 31: DVF Description 0 ...
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Operation Description 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers ...
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Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of ...
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When the data value is included in the break conditions on B channel: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle ...
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When data access (address + data) is specified as a break condition: The PC value is the start address of the instruction that follows the instruction already executed when break processing started up. When a data value is added ...
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BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in ...
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Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel ...
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Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel ...
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Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel ...