CY7C024-15AI Cypress Semiconductor Corporation., CY7C024-15AI Datasheet
CY7C024-15AI
Specifications of CY7C024-15AI
Related parts for CY7C024-15AI
CY7C024-15AI Summary of contents
Page 1
... CY7C025/0251 to handle situations when multiple pro- cessors access the same piece of data. Two ports are provid- ed, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/0241 and CY7C025/0251 can be utilized as standalone 16-/18-bit du- al-port static RAMs or multiple devices can be combined in order to function as a 32-/36-bit or wider master/slave du- = 150 mA (typ ...
Page 2
... I/O 8L 15L [2] I/O – I [1] BUSY L (CY7C025/0251) A 12L A 11L A 0L R/W L SEM L INT L Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 I/O I/O CONTROL CONTROL MEMORY ADDRESS ARRAY DECODER INTERRUPT CE SEMAPHORE L ARBITRATION M/S 2 ...
Page 3
... TQFP Top View CY7C024 CY7C024/0241 CY7C025/0251 ...
Page 4
... Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground 4 CY7C024/0241 CY7C025/0251 ...
Page 5
... One Port CE or Com’ – 0.2V Ind V V – 0. 0.2V [7] Active Port Outputs MAX 5 CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251– 160 150 Ambient Temperature + – + 7C024/0241– ...
Page 6
... MHz 5. 250 TH OUTPUT C = 30pF V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 0.4 0.4 2.2 2.2 –0.7 0.8 –0.7 0.8 –10 +10 –10 +10 –10 +10 – ...
Page 7
... HZCE LZCE HZOE 7 CY7C024/0241 CY7C025/0251 7C024/0241–55 7C025/0251–55 Min. Max. Min. Max. Unit ...
Page 8
... BDD Data Retention Mode The CY7C024/0241 is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
Page 9
... LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C024/0241 CY7C025/0251 t OHA DATA VALID 7C024–14 t HZCE t HZOE DATA VALID t PD 7C024–15 t OHA t HZCE t HZCE 7C024–16 . ...
Page 10
... SD [23, 24, 25, 31 SCE LOW CE or SEM and a LOW PWE HZWE . CY7C024/0241 CY7C025/0251 [29] t HZOE LZWE NOTE 7C024– 7C024– allow the I/O drivers to turn off and data to be placed on SD ...
Page 11
... SPS [32 SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C024/0241 CY7C025/0251 OHA VALID ADRESS t ACE DATA VALID OUT t DOE 7C024–19 7C024–20 ...
Page 12
... R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW [36 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C024/0241 CY7C025/0251 BHA t BDD t DDD VALID 7C024–21 7C024–22 ...
Page 13
... BUSY will be asserted. PS [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 13 CY7C024/0241 CY7C025/0251 t BHC 7C024–23 t BHC 7C024–24 7C024–25 7C024–26 ...
Page 14
... INS INR [38 [39] t INR t WC [38 [39] t INR ) is deasserted first R asserted last CY7C024/0241 CY7C025/0251 7C024– READ FFF (1FFF CY7C025) 7C024–28 7C024– READ FFE (1FFE CY7C025) 7C024–30 ...
Page 15
... When reading the device, the user must assert both the OE and CE pins. Data will be available t after ACE asserted. If the user of the CY7C024/0241 or CY7C025/0251 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing ...
Page 16
... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free 16 CY7C024/0241 CY7C025/0251 [3] –I/O Operation 8 15 Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only ...
Page 17
... CY7C024–15AC CY7C024–15JC 25 CY7C024–25AC CY7C024–25JC CY7C024–25AI CY7C024–25JI 35 CY7C024–35AC CY7C024–35JC CY7C024–35AI CY7C024–35JI 55 CY7C024–55AC CY7C024–55JC CY7C024–55AI CY7C024–55JI Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C025–15AC CY7C025–15JC CY7C025–15AI 25 CY7C025–25AC CY7C025– ...
Page 18
... Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C0241–15AC CY7C0241–15AI 25 CY7C0241–25AC CY7C0241–25AI 35 CY7C0241–35AC CY7C0241–35AI 55 CY7C0241–55AC CY7C0241–55AI Ordering Information (continued Dual-Port SRAM Speed Package (ns) Ordering Code 15 CY7C0251–15AC 25 CY7C0251–25AC CY7C0251–25AI 35 CY7C0251–35AC CY7C0251– ...
Page 19
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Plastic Leaded Chip Carrier J83 CY7C024/0241 CY7C025/0251 51-85048-A ...