MT9079AL Zarlink Semiconductor, MT9079AL Datasheet
MT9079AL
Related parts for MT9079AL
MT9079AL Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2006, Zarlink Semiconductor Inc. All Rights Reserved. CMOS ST-BUS MT9079AE MT9079AL MT9079AP MT9079APR MT9079AL1 MT9079AP1 MT9079APR1 • CO and PABX switching equipment interfaces • E1 add/drop multiplexers and channel banks • ...
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... CSTi2 9 37 VSS TxMF 12 34 RxMF 13 33 DSTi 14 32 E8Ko 15 31 F0i 16 30 RxA 17 29 RxB 44 PIN PLCC Figure 2 - Pin Connection 2 Zarlink Semiconductor Inc. Data Sheet CSTi2 31 VSS 30 S/P 29 TxMF 28 RxMF 27 DSTi 26 E8Ko 25 F0i 24 RxA 23 RxB 44 PIN QFP ...
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... Address/Control 4 (Input): The most significant address and control input for the [P] non-multiplexed parallel processor interface. ST/SC ST-BUS/Serial Controller (Input): High - selects ST-BUS mode of operation. [ST S] Low - selects serial controller mode of operation. MT9079 Description (see notes 1, 2 and 3) 10%. 3 Zarlink Semiconductor Inc. Data Sheet through a pull-up resistor. DD ...
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... Receives RZ and NRZ bipolar signals. See Figurs 29 and 31 F0i Frame Pulse (Input): This is the ST-BUS frame synchronization signal which delimits the 32 channel frame of all ST-BUS streams, as well as DSTi and DSTo in all modes. MT9079 Description (see notes 1, 2 and 3) 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Note: 2.All outputs are CMOS and are compatible with both TTL and CMOS logic levels. Note: 3.See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for input and output voltage thresholds. MT9079 Description (see notes 1, 2 and 3) 5 Zarlink Semiconductor Inc. Data Sheet When ...
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... The functionality of the MT9079 has been heighten with the addition of a comprehensive set of maskable interrupts and an interrupt vector function. Interrupt sources consist of synchronization status, alarm status, counter indication and overflow, timer status, slip indication, maintenance functions and receive channel associated signalling bit changes. MT9079 6 Zarlink Semiconductor Inc. Data Sheet ...
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... CRC-4 polynomial (multiplied by X generates a four bit remainder. This remainder is inserted in bit position one of the four FASs of the following MT9079 .... .... are national bits, which telephone authorities used to communicate Zarlink Semiconductor Inc. Data Sheet 4 4 then divided 1), which ...
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... It should be noted that in this mode access to the circular buffers and notional bit buffers is not provided, and the MT9079 = 0, a CRC-4 error was discovered in a submultiframe CRC-4 error was discovered in a submultiframe two received at the far 2 8 Zarlink Semiconductor Inc. Data Sheet ...
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... CSTo1 SERIAL P IRQ RxD ST/SC SIO CONTROL CS INTERFACE SCLK +5V S/P CSTi2 CSTo1 ST-BUS CSTo0 +5V ST/SC CONTROL CSTi0 INTERFACE CSTi1 +5V S/P CSTi2 CSTo1 Figure 3 - Control Port Interface = data transfer within the current memory 4 9 Zarlink Semiconductor Inc. Data Sheet data byte (when ...
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... Receive National Bit Buffer MT9079 Register Description Master Control Master Status Per Time Slot Control Table 2 - Register Summary 10 Zarlink Semiconductor Inc. Data Sheet Processor/ ST-BUS Controller Access Access R/W CSTi0 R/W R CSTo0 R/W R/W CSTi2 R CSTo1 R/W CSTi1 R/W R/W --- R/W --- ...
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... Code Insert/Detect Deactivated Signalling CAS (CSTi2 & CSTo1) Deactivated Interrupt Mask Word Zero unmasked, all others Interrupts masked; interrupts not suspended RxMF Output Signalling Multiframe Error Insertion Deactivated Coding 10* Tx/Rx Buffers Deactivated Counters Random Table 3 - Reset Status 11 Zarlink Semiconductor Inc. Data Sheet ...
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... X 12 Zarlink Semiconductor Inc. Data Sheet ...
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... E 1 ALM 14/FAS 15/NFAS E 1 ALM Table 4 - FAS and NFAS Structure 13 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 5 - MT9079 National Bit Buffers bit used for the DL is selected by making one Zarlink Semiconductor Inc. Data Sheet F11 F13 F15 ...
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... If bit two of the NFAS is zero a new search for basic frame alignment is initiated. If bit two of the NFAS is one and the next FAS is correct, the algorithm declares that basic frame synchronization has been found (i.e., SYNC is low). MT9079 Read Pointer -13 CH Read Pointer 15 Zarlink Semiconductor Inc. Data Sheet Wander Tolerance ...
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... When CRC-4 multiframing has been achieved, the primary basic frame alignment and resulting multiframe alignment will be adjusted to the basic frame alignment determined during CRC-4 synchronization. Therefore, the primary basic frame alignment will not be updated during the CRC-4 multiframing search, but will be updated when the CRC-4 multiframing search is complete. MT9079 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Notes 6 & 7. 400 msec timer expired CRC-to-non-CRC interworking. Maintain primary basic frame alignment. Continue to send CRC-4 data, but stop CRC processing. E-bits set to ‘0’. Indicate CRC-to-non-CRC 17 Zarlink Semiconductor Inc. Data Sheet NO 3 consecutive incorrect frame alignment signals NO ...
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... Bit PLBK = 0 normal; PLBK = 1 activate. The payload loopback is effectively a physical connection of DSTo to DSTi within the MT9079. Channel zero and the DL originate at the point of loopback. MT9079 MT9079 DSTi Tx PCM30 DSTo MT9079 Tx PCM30 DSTo Rx MT9079 DSTi Tx PCM30 DSTo respectively at the system side with FAS and NFAS 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Overflow interrupts are useful when cumulative error counts are being recorded. For example, every time the frame error counter overflow interrupt (FERO) occurs, 256 frame errors have been received since the last FERO interrupt. MT9079 MT9079 DSTi Tx PCM30 DSTo Rx MT9079 Tx DSTi PCM30 DSTo Rx 19 Zarlink Semiconductor Inc. Data Sheet ...
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... There are two maskable interrupts associated with the CRC error and E-bit error measurement. CRCI and EBI are initiated when the least significant bit of the appropriate counter toggles, and CRCO and EBO are initiated when the appropriate counter changes from FFH to 00H. MT9079 20 Zarlink Semiconductor Inc. Data Sheet ...
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... T is the elapsed time in seconds. This assumes that one BPV error will be the result of one bit error. MT9079 BERT estimation = BERT counter value/(N BERT estimation = CEt counter value/(2048000 8000 Zarlink Semiconductor Inc. Data Sheet 4000 T ...
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... This user-defined bit pattern is determined by the Code Detect Word (CDW) and Detect Word Mask (CDM) mentioned below. The functionality and control of the START and STOP interrupts is described in Table 6. MT9079 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Circular buffer zero starts recording on a match with CDW and CDM. Circular buffer one starts recording on a match with CDW and CDM. Circular buffer zero starts recording on a mismatch with CDW and CDM. Circular buffer one starts recording on a mismatch with CDW and CDM. 23 Zarlink Semiconductor Inc. Data Sheet ...
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... When AUTY = 0 and signalling multiframe alignment is not acquired (MFSYNC = 1), the MT9079 will automatically transmit the multiframe alarm (Y-bit) signal to the far end of the link. This transmission will cease when signalling multiframe alignment is acquired. MT9079 24 Zarlink Semiconductor Inc. Data Sheet ...
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... All the interrupts of the MT9079 are maskable. This is accomplished through interrupt mask words zero to four, which are located on page 1, addresses 1BH to 1EH. After a MT9079 reset (RESET pin or RST control bit) all interrupts of mask words one, two and three are masked; and the interrupts of mask word zero are unmasked. MT9079 25 Zarlink Semiconductor Inc. Data Sheet ...
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... MFSYI CSYNI RFALI YI 1SEC STOP All interrupts may be suspended, without changing the interrupt mask words, by making the SPND control bit of page 1, address 1AH high. MT9079 Bit 0 FERI BPVO SLPI Bit 0 BERI --- SIGI Bit 0 --- Bit 0 STRT DATA 26 Zarlink Semiconductor Inc. Data Sheet ...
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... RDLY, SPND,TxCAS, RPSIG & BFAS SYNI, RAII, AISI, AIS16I, LOSI, FERI, BPVO & SLPI EBI, CRCI, CEFI, BPVI, RCRI, BERI & SIGI EBO, CRCO, CALNI, FERO, RCRO, BERO & AUXPI MFSYI, CSYNI, RFALI, YI, 1SEC, STOP, STRT & DATA --- 27 Zarlink Semiconductor Inc. Data Sheet Function - ...
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... CRCT, EBT, 400T, 8T & CALN RIU1, RNFAB, RALM & RNU4-8 RMA1-4, X1 & X3 RSLIP, RSLPD, AUXP, CEFS, RxFRM & RxTS4-2 RxTS1-0, RxBC2-0 & RxEB2-0 --- CRCS1, CRCS2, RFAIL, LOSS, AIS16S, AISS, RAIS & RCRS --- 28 Zarlink Semiconductor Inc. Data Sheet Function Function ...
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... signalling bits associated with channel n + 15. D(n+15) Table 12 - Transmit Channel Associated Signalling (Page 5) MT9079 Register --- IV7 - IV0 --- BR7 - BR0 RCRC7 - RCRC0 EFAS7 - EFAS0 --- BPV15 - BPV8 BPV7 - BPV0 EC7 - EC0 CC7 - CC0 Functional Description 29 Zarlink Semiconductor Inc. Data Sheet Function ...
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... C(n) are the signalling bits associated with channel n. & D( --- Same as bits 7-4. Table 16 - Receive CAS Channels (CSTo1) MT9079 Functional Description Functional Description Functional Description Functional Description 30 Zarlink Semiconductor Inc. Data Sheet ...
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... If zero, circular buffer one will not connected to this time slot. This buffer is accessible only in processor and controller modes. Table 18 - Per Time Slot Control Words MT9079 Functional Description Functional Description (Pages 7 and 8) (continued) 31 Zarlink Semiconductor Inc. Data Sheet ...
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... Receive Bits This byte is received from a time slot selected by the RBUF1 bit of the - appropriate per time slot control words and represents a byte position in receive circular buffer one (RxB1). RxB1.n .0 Table 22 - Receive Circular Buffer One (Page C) MT9079 Functional Description Functional Description Functional Description Functional Description 32 Zarlink Semiconductor Inc. Data Sheet . ...
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... Table 25 - Multiframe, National Bit Buffer and DL Selection Word MT9079 Functional Description Bits Frames 1 to 15. This byte contains the bits transmitted in bit position an+4 Functional Description Bits Frames 1 to 15. This byte contains the bits received in bit position n+4 an+4 Functional Description (Page 1, Address 10H) 33 Zarlink Semiconductor Inc. Data Sheet ...
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... See Sa4 - Sa8 control bits of the DL selection word (page 1, address 10H). MT9079 Functional Description (Page 1, Address 11H) Functional Description Table 27 - TNFA Control Word (Page 1, Address 12H) 34 Zarlink Semiconductor Inc. Data Sheet ARAI is zero ...
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... ST-BUS control and data streams. The input streams are always aligned with F0i and the SOFF0 output streams may be delayed by as much as 255 bits. (00H)* Table 29 - ST-BUS Offset Control Word MT9079 Functional Description AUTY is zero (page 1, address 11H). (Page 1, Address 13H) Functional Description (Page 1, Address 14H) 35 Zarlink Semiconductor Inc. Data Sheet ...
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... ST-BUS side of the MT9079 (this excludes time slot zero). If zero, then this feature is disabled. See Loopbacks section. Table 30 - Coding and Loopback Control Word (Page 1, Address 15H) MT9079 Functional Description Function HDB3 encoding is enabled in the transmit direction. HDB3 encoding is transmitted. 36 Zarlink Semiconductor Inc. Data Sheet HDB3 is always decoded in the receive ...
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... Time slots are selected for comparison by the CDDTC bit of the per time slot control word. (00H match is found a maskable interrupt (Data) can be initiated. MT9079 Functional Description (Page 1, Address 16H) Functional Description Table 32 - Code Insert Word (Page 1, Address 17H) Functional Description Table 33 - Code Detect Word (Page 1, Address 18H) 37 Zarlink Semiconductor Inc. Data Sheet ...
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... FAS will increment the Bit Error Rate Counter (BERC). If one, bit errors in the comparison between receive circular buffer one and the bit error rate compare word will be counted --- Unused. Table 35 - Interrupt, Signalling and BERT Control Word MT9079 Functional Description (Address 19H) Functional Description (Page 1, Address 1AH) 38 Zarlink Semiconductor Inc. Data Sheet ...
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... FFFFH to 0H unmasked masked. Interrupt vector = 00010000. 0 SLPI SLIP Interrupt. When unmasked an interrupt is initiated when a controlled frame slip occurs unmasked masked. Interrupt vector = 00000100. Table 36 - Interrupt Mask Word Zero MT9079 Functional Description (Page 1, Address 1BH 39 Zarlink Semiconductor Inc. Data Sheet ...
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... Auxiliary Pattern Interrupt. When unmasked an interrupt is initiated when the AUXP status (0) bit of page 3, address 15H goes high unmasked masked. Interrupt vector = 01000000. 0 --- Unused. Table 38 - Interrupt Mask Word Two MT9079 Functional Description (Page 1, Address 1CH) Functional Description (Page 1, Address 1DH) 40 Zarlink Semiconductor Inc. Data Sheet ...
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... Data Interrupt. When unmasked an interrupt is initiated when the data received in selected (0) time slots (per time slot control words) matches the data in the code detect word (CDW unmasked masked. Interrupt vector = 00000010. Table 39 - Interrupt Mask Word Three MT9079 Functional Description (Page 1, Address 1EH) 41 Zarlink Semiconductor Inc. Data Sheet ...
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... When individual bit mismatches are detected the Bit Error Rate Counter (BERC) (00H) is incremented. Table 41 - Bit Error Rate Compare Word MT9079 Functional Description HDB3 encoding is activated no violations are transmitted. If (Page 2, Address 10H) Functional Description (Page 2, Address 11H) 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Error Rate Load Word. Data is loaded into the eight bit BER counter when this bit is (0) changed from low to high. Table 43 - Counter Load Control Word MT9079 Functional Description Functional Description (Page 2, Address 15H) (Valid in ST-BUS mode only) 43 Zarlink Semiconductor Inc. Data Sheet ...
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... E-bit Error Counter Load Word. This bit pattern is loaded into the E-bit error counter when - LDEC is toggled (valid in ST-BUS mode only). ECLD0 Table 49 - E-bit Error Counter Load Word MT9079 Functional Description (Page 2, Address 18H) Functional Description Functional Description Functional Description Functional Description Functional Description (Page 2, Address 1EH) 44 Zarlink Semiconductor Inc. Data Sheet ...
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... These bits form the frame alignment signal and should be 0011011. Table 52 - Receive Frame Alignment Signal MT9079 Functional Description (Page 2, Address 1FH) Functional Description (Page 3, Address 10H) Functional Description (Page 3, Address 11H) 45 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 55 - Receive Multiframe Alignment Signal (Page 3, Address 14H) MT9079 Functional Description Table 53 - Timer Status Word (Page 3, Address 12H) Functional Description Functional Description 46 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz. The accuracy of the this mea- surement is approximately + 1/16 (one sixteenth bit. Table 57 - Least Significant Phase Status Word MT9079 Functional Description -3 . (Page 3, Address 15H) Functional Description (Page 3, Address 16H) 47 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 58 - Alarm Status Word One (Page 3, Address 19H) (continued) Functional Description Table 59 - Interrupt Vector Status Word (Page 4, Address 12H) Functional Description BFAS Table 60 - Bit Error Rate Counter (Page 4, Address 18H) 48 Zarlink Semiconductor Inc. Data Sheet control bit function of page 1, address 1AH. ...
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... CRC-4 error counter. CC0 MT9079 Functional Description (Page 4, Address 19H) Functional Description (Page 4, Address 1AH) Functional Description (Page 4,Address 1CH) Functional Description Functional Description (Page 4, Address 1EH) Functional Description Table 66 - RC-4 Error Counter CEt (Page 4, Address 1FH) 49 Zarlink Semiconductor Inc. Data Sheet ...
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... MISO MOSI SCK SS Figure 7 - MT9079 to MC68HC11 (2.1 MHz) Microcontroller Interface Circuit MT9079 . The remainder of this interface is similar to the MC68HC11 RWS 3 CS 74HCT04 +5V 4.7k IRQ R/W 74HCT04 DS S/P TxDL RxDL DLCLK 50 Zarlink Semiconductor Inc. Data Sheet - AD are used 0 7 MT9079 - ...
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... MT9079 devices transmit AIS during system initialization; and 3) to have all the MT9079 devices transmit AIS when the MC68302 watch-dog time expires. MT9079 74HCT04 74HCT74 74HCT08 74HCT04 74HCT04 +5V 10k PR 74HCT74 D Q CLR 3 74HCT04 5 8 +5V 10k 51 Zarlink Semiconductor Inc. Data Sheet MT9079 DS S/P R IRQ DLCLK RxDL TxDL ...
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... 74F04 74F74 74F86 Q D 74F04 Q CLR 74F04 +5V 10k 74F04 52 Zarlink Semiconductor Inc. Data Sheet MT9079 CS IRQ DS R S/P RxDL TxDL DLCLK MT9079 - S/P DS R/W CS IRQ ...
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... RESET 74HCT05 MT9079 74HCT11 TAIS to Control Port RESET MT9079 74HCT11 TAIS to Control Port RESET . . . . . . . . MT9079 74HCT11 TAIS to Control Port RESET 53 Zarlink Semiconductor Inc. Data Sheet +5V +5V +5V 4.7k 4.7k 4.7k 74HCT05 74HCT74 74HCT05 CLR CLR 74HCT32 PCM 30 Trunk 0 PCM 30 Trunk 1 PCM 30 ...
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... Clear the error counters of page 4. Note 2. Read interrupt vector register, page 4. Note 3. SPND = 0. Note 3. TAIS input = high STOP Figure 12 - MT9079 Initialization Procedure 54 Zarlink Semiconductor Inc. Data Sheet TE bit = 1 Notes: 1. Skip if default option is required. 2. Skip if counters are not used. 3. Skip if interrupts are not used. ...
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... C2 is used to clock data into and out of the NMSI1 port. MT9079 LIU EC3 to EC2 Control EC1 Port RLOOP MT9079 DSTi TxA DSTo TxB RxA F0i RxB C4i/C2i E8ko E2i RCLK TCLK Figure 13 - PCM 30 Line Interface Unit (LIU) 55 Zarlink Semiconductor Inc. Data Sheet Trunk Interface E1 Transmit E1 Receive ...
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... Therefore frame delay circuit is added to the TxMF to RxMF connection (where the delay in basic frames through the Digital Cross-Connect Matrix). MT9079 100 DSTi DSTo 100 MT9079 P Interface Address Data C2 & Control MC68302 56 Zarlink Semiconductor Inc. Data Sheet MT9079 C4i/C2i TxA To Trunk Interface TxB RxA RxB E2i a4 ...
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... Table 67 - 2.048 Mbit/sec. Interface Configurations MT9079 Digital Cross-Connect Matrix MT8980D MT8980D STi0 STo0 Switch 0,0 Switch 0,M m+1 Frame Delay MT8980D MT8980D Switch n,0 Switch n,M 57 Zarlink Semiconductor Inc. Data Sheet MT9079 TxA DSTo TxB DSTi To Line C4i/C2i C4 Interface RxA RxB E2i RxMF TxMF To Data Link ...
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... NRZ signal and a receive clock. MT9079 DSTi C4i/C2i DSTo TxA TxB RxA RxB E2i MT9079 C4 C2 Manchester Encoder Transmit Fibre Interface Tx+ CLKi Tx+ NRZ Tx- Datai Tx- Manchester Decoder Receive Fibre Interface NRZ Data0 RxData CODEi RxCLK 58 Zarlink Semiconductor Inc. Data Sheet Transmit Fibre Receive Fibre ...
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... MT9079 Figure 16 - MT9079 Fibre Interface Circuit 59 Zarlink Semiconductor Inc. Data Sheet ...
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... Sym. Level Units 2 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - -65 150 °C 800 mW ) unless otherwise stated. Units Conditions/Notes °C V Units Conditions/Notes mW Outputs unloaded ...
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... DAZ DSW DHW . Timing is corrected to cancel time taken to discharge C L Timing parameters are measured with respect to both CMOS 61 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes See Note 3 See Note 3 C =150pF See Note 2 C =150pF See Notes 1, 2 & 4 ...
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... DSH DS CS R/W A0-A4 D0-D7 READ D0-D7 WRITE Figure 17 - Microprocessor Timing Diagram MT9079 t DSL t CSS t RWS t ADS t DDR VALID DATA t DSW VALID DATA 62 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DAZ DHW V TT ...
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... AZD bit 0 bit bit 7 bit 7 bit bit 0 63 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes SCLK period = 500 ns SCLK period = 500 ns C =150 =150pF CSH V bit AZD V TT, ...
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... DOD t 20 DLS t 30 DLH Channel 0, Bit 3 Channel 0, Bit 2 t DCD t DOD Channel 16, Bit 3 Channel 16, Bit 2 t DCD t t DLS DLH 64 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes ns 150 pF, See Note 1 ns 150 TT TT ...
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... SIH t SOD Channel 0, Bit 7 Channel 0, Bit 6 t FPL t t FPS 2W t SIH t SIS SOD Figure 22 - ST-BUS Timing Diagram 65 Zarlink Semiconductor Inc. Data Sheet Max. Units Conditions/Notes 258 ns C2i clock period = 458 ns 159 ns C4i clock period = 244 150pF V TT ...
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... Typ. t MOD 100 MH2 Bit 4 Bit 0 Bit 7 Bit 6 Frame N Bit 4 Bit 0 Bit 7 Bit 6 66 Zarlink Semiconductor Inc. Data Sheet Max. Units Conditions/Notes 75 ns 150 256 C2 periods -100 nsec ns Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0 Bit 5 Bit 4 Bit 0 ...
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... MOD t (1) RxMF (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 26 - Multiframe Timing Diagram (C4i/C2i = 4.096 MHz) MT9079 t MOD t MH MOD 67 Zarlink Semiconductor Inc. Data Sheet TT MH2 TT MH2 V TT ...
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... Figure 27 - E8Ko Timing Diagram Sym. Min. Typ. Max TDN t 75 TDR Bit Cell t t TDR TDR t TDN Figure 28 - PCM 30 Transmit Timing 68 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes ns 150 pF s 62.5 sec typical Time slot 0 Bit ...
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... MT9079 Sym. Min. Typ CPW Bit Cell t CPW CPW Figure 29 - PCM 30 Receive Timing Figure 30 - Transmit Functional Timing 69 Zarlink Semiconductor Inc. Data Sheet Max. Units Conditions/Notes 438 ns E2i clock period = 488 nsec TT, CT ...
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... FRAME 14 TIME SLOT • • • • 1 125 s BIT BIT BIT BIT BIT (8/2.048) s Figure 32 - PCM 30 Format 70 Zarlink Semiconductor Inc. Data Sheet FRAME FRAME 15 0 TIME SLOT TIME SLOT 30 31 Least BIT BIT Significant 7 8 Bit (Last) ...
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... CHANNEL 0 31 Most BIT Significant 7 Bit (First) Figure 33 - ST-BUS Stream Format MT9079 125 s CHANNEL • • • 30 BIT BIT BIT BIT BIT (8/2.048 Zarlink Semiconductor Inc. Data Sheet CHANNEL CHANNEL 31 0 Least BIT BIT Significant 0 1 Bit (Last) ...
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