ADM6996L Infineon Technologies AG, ADM6996L Datasheet
ADM6996L
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ADM6996L Summary of contents
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... An Infineon Technologies Company ADM6996L 6 port 10/100 Mb/s Single Chip Ethernet Switch Controller Infineon-ADMtek Co Ltd Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. Infineon- ADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” ...
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... November 2003 12 January 2004 28 April 2004 Customer Support Infineon-ADMtek Co Ltd, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 Version Change 1.0 1. First release of ADM6996L 1.01 2. Updated Section 1.1 and 2.2.2 1.02 3. Updated Section 4.3.12 & 3.4 1.03 4. Updated Section 5.3 1.04 Updated Infineon-ADMtek logo V1.04 ...
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... Data De-scrambling................................................................................. 3-3 3.4.5 Symbol Alignment .................................................................................... 3-3 3.4.6 Symbol Decoding ..................................................................................... 3-3 3.4.7 Valid Data Signal..................................................................................... 3-3 3.4.8 Receive Errors ......................................................................................... 3-4 3.4.9 100Base-X Link Monitor.......................................................................... 3-4 3.4.10 Carrier Sense ........................................................................................... 3-4 3.4.11 Bad SSD Detection................................................................................... 3-4 3.4.12 Far-End Fault .......................................................................................... 3-5 3.5 100Base-TX Transceiver ................................................................................. 3-5 3.5.1 Transmit Drivers...................................................................................... 3-5 3.5.2 Twisted-Pair Receiver.............................................................................. 3-5 3.6 10Base-T Module............................................................................................. 3-5 3.6.1 Operation Modes ..................................................................................... 3-6 3.6.2 Manchester Encoder/Decoder ................................................................. 3-6 3.6.3 Transmit Driver and Receiver ................................................................. 3-6 3.6.4 Smart Squelch .......................................................................................... 3-6 3.7 Carrier Sense.................................................................................................... 3-7 ADM6996L V1.04 i ...
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... Port0, 1 PVID bit Configuration Register, offset: 0x28h ............. 4-1 4.3.17 Port2, 3 PVID bit Configuration Register, offset: 0x29h ............. 4-1 4.3.18 Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah ............... 4-1 4.3.19 Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-1 4.3.20 Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register.. 4-1 ADM6996L V1.04 ii ...
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... MII Output Timing ................................................................ 5-4 5.3.5 100Base-TX MII Input Timing ................................................................. 5-5 5.3.6 100Base-TX MII Output Timing .............................................................. 5-5 5.3.7 GPSI(7-wire) Input Timing ...................................................................... 5-6 5.3.8 GPSI(7-wire) Output Timing ................................................................... 5-6 Chapter 6 Packaging...................................................................................................... 6-1 6.1 128 Pin PQFP Outside Dimension................................................................... 6-1 Figure 1-1 ADM6996L Block Diagram .......................................................................... 1-3 Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram.......................................... 2-1 ADM6996L List of Figures V1.04 iii ...
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... Control Pause packet in Full-Duplex mode to prevent packet lost when buffer full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the ADM6996L will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode. ...
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... Support PHY status output for management system. x 25M Crystal only for the whole system. x 128 QFP package with 0.18um technology. 1.8V/3.3V power supply. x 1.3 Applications ADM6996L in 128-pin PQFP: Infineon-ADMtek Co. Ltd. SOHO 5-port switch 5-port switch + Router with MII CPU interface. Product Review 1-2 ...
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... PORT2 ... PORTN A/D DIGITAL CONVERTER EQUALIZER DRIVER MLT3 Converter BIAS CLOCK GENERATOR Figure 1-1 ADM6996L Block Diagram Bit Error Rate Canonical Format Indicator Collision Cyclic Redundancy Check Carrier Sense Chip Select Destination Address Data Input Data Output EEPROM Data Input EEPROM Data Output ...
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... ADM6996L EESK ESD FEFI FET FLP GND GPSI IPG LFSR MAC MDIX MII NRZI NRZ PCS PHY PLL PMA PMD QoS QFP RST RXCLK RXD RXDV RXER RXN RXP SA SOHO SSD SQE TOS TP TTL TXCLK TXD TXEN TXN TXP Infineon-ADMtek Co. Ltd. ...
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... ADM6996L 1.6 Conventions 1.6.1 Data Lengths qword dword word byte nibble 1.6.2 Pin Types Pin Type I O I/O OD SCHE PD PU 1.6.2 Register Types Register Type Infineon-ADMtek Co. Ltd. 64-bits 32-bits 16-bits 8 bits 4 bits Description Input Output Bi-directional Open drain Schmitt Trigger internal pull-down internal pull-up Description ...
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... GNDBIAS 120 RTX 121 VCCBIAS 122 VCCA2 123 TXP0 124 TXN0 125 GNDA 126 RXP0 127 RXN0 128 VCCAD Infineon-ADMtek Co. Ltd. ADM6996L Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram Interface Description 64 GNDIK 63 (GFCEN) TXD0 62 P4FX 61 TXD1 60 TXD2 59 TXD3 58 LDSPD4 57 GNDO 56 VCC3O ...
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... ADM6996L 2.2 Pin Description by Function ADM6996L pins are categorized into one of the following groups: ƒSection 2.2.1 Twisted Pair Interface ƒSection 2.2.2 6th Port (MII) Interfaces ƒSection 2.2.3 LED Interface ƒSection 2.2.4 EEPROM/Management Interface ƒSection 2.2.5 Power/Ground, 48 pins ƒSection 2.2.6 MISC Note: “Section 1.6.2 Pin Types” can be used for reference. ...
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... ADM6996L Pin Name P4FX XEN Setting PHYAS0 RXD[0] RXD[3:1] 102, 101, RXDV RXER COL CRS RXCLK TXCLK DHALFP5 LNKFP5 SPDTNP5 Infineon-ADMtek Co. Ltd. Pin# Type Descriptions 8mA Synchronous to the rising edge of TXCLK. These pins act PD as MII TXD[3:2 Port4 FX/TX mode select. Internal pull down. ...
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... ADM6996L 2.2.3 LED Interface Pin Name LNKACT[4:0] 92, 95, 96, 97, 98 DUPCOL[4:3] 103, 106 DUPCOL2 Setting BPEN DUPCOL1 Setting PHYAS1 DUPCOL0 Setting ANEN LDSPD[4:0] 58, 55, 54, 51, 50 Infineon-ADMtek Co. Ltd. Pin# Type Descriptions O, LINK/Activity LED[4:0]. Active low 8mA “1” indicates no link activity on cable “0” indicates link okay on cable, but no activity and signals on idle stage. “ ...
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... ADM6996L 2.2.4 EEPROM/Management Interface Pin Name EDO EECS EECK Setting XOVEN EDI Setting LEDMODE 2.2.5 Power/Ground, 48 pins Pin Name GNDA 3, 10, 16, 23, 29, 36, 42, 125 VCCA2 6, 7, 19, 20, 32, 33, 45, 122 VCCAD 13, 26, 39, 128 GNDBIAS VCCBIAS GNDPLL VCCPLL GNDIK 47, 52, 64, 76, 93, 83, VCCIK 48, 53, 65, ...
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... ADM6996L 2.2.6 MISC Pin Name CKO25M Control RTX VREF CFG0 TEST 4,5, 14, 15,17, 18, 27,28, Infineon-ADMtek Co. Ltd. Pin# Type Descriptions 85 O, 25M Clock Output. 8mA 117 O FET Control Signal. The pin is used to control FET for 3.3V to 1.8V regulator. 120 Analog TX Resistor. Add 1.1K %1 resister to GND. 118 Analog Analog Reference Voltage ...
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... Module The ADM6996L implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100Mbits/s PHY loop back is included for diagnostic purpose. ...
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... Decision Feedback techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 120 meters. 3.4.3 NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary. Infineon-ADMtek Co. Ltd. The ADM6996L implements the 100Base-X Function Description 3-2 ...
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... Symbol Alignment The symbol alignment circuit in the ADM6996L determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de- scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary ...
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... If this condition is detected, then the ADM6996L will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code- groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become de-asserted ...
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... The ADM6996L uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable ...
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... Jabber and SQE test functions x Polarity detection and correction 3.6.1 Operation Modes The ADM6996L 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the ADM6996L functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive ...
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... CRS is asserted only due to receive activity. 3.8 Jabber Function The jabber function monitors the ADM6996L output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... Memory Block ADM6996L build in memory is divided as two blocks. One is MAC addressing table and another one is data buffer. MAC address Learning Table size is 2048 entry with each entry occupy eight bytes length. These eight bytes data include 6 bytes source address, VLAN information, Port information and Aging counter ...
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... Address is not found in the Address Table, the device adds it to the table. 3.15.1 Address Learning The ADM6996L uses a hash algorithm to learn the MAC address and can learn MAC addresses. Address is stored in the Address Table. The ADM6996L searches for the Source Address (SA incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the ADM6996L waits until the end of the packet (non-error packet) and updates the Address Table ...
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... Address Aging Address aging is supported for topology changes such as an address moving from one port to the other. When this happens, the ADM6996L internally has a 300 seconds timer will aged out (remove) the address from the address table. Aging function can enable/disable by user. Normally, disabling aging function is for security purpose. ...
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... CRC. Dribbling packing with good CRC value will accept by ADM6996L. In case of bypass mode enabled, ADM6996L will support tag and untagged packets with size up to 1522 bytes. In case of non-bypass mode, ADM6996L will support tag packets up to 1526bytes, untagged packets up to 1522bytes ...
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... ADM6996L also supports 16 802.1Q VLAN groups. In VLAN four bytes tag include twelve VLAN ID. ADM6996L learn user define four bits of VID. If user need to use this function, two EEPROM registers are needed to be programmed first : * Port VID number at EEPROM register 0x01h~0x09h bit 13~10, register 0x28h~0x2bh and register 0x2ch bit 7~0: ADM6996L will check coming packet ...
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... VLAN and TOS VLAN first: ADM6996L check VLAN three priority bit first then IP TOS priority bits TOS first: ADM6996L check IP TOS three priority bit first then VLAN three priority bits. If port set at VLAN/TOS priority but receiving packet without VLAN or TOS information then port base priority will be used ...
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... ADM6996L ADM6996L LED is active Low signal. Dupcol0 & Dupcol1 will check external signal at Reset time. If external signal add pull high then LED will active Low. If external signal add pull down resister then LED will drive high. Link /Ac t Infineon-ADMtek Co. Ltd. Single ...
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... ADM6996L Chapter 4 Register Description 4.1 EEPROM Content EEPROM provides ADM6996L many options setting such as: x Port Configuration: Speed, Duplex, Flow Control Capability and Tag/ Untag. x VLAN & TOS Priority Mapping x Broadcast Storming rate and Trunk. x Fiber Select, Auto MDIX select x VLAN Mapping x Per Port Buffer number 4 ...
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... RO The value must be 4154h(AT) Note: ADM6996L will check register 0 value before read all EEPROM content. If this value not match with 0x4154h then other values in EEPROM will be useless. ADM6996L will use internal default value. User cannot write Signature register when programming ADM6996L internal register. ...
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... R/W Enable port-base priority. 1: Port Base Priority. 0: VLAN or TOS. If packet without VLAN or TOS then port priority turn on. Note: If this bit turn on then ADM6996L will not check TOS or VLAN as priority reference. ADM6996L will check port base priority only. ADM6996L default is bypass mode which checks port base priority only. ...
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... Type Description 5:0 RO Reserved 6 R/W Enable IPG leveling. 1/92 bit. 0/96 bit. Note: When this bit is enable ADM6996L will transmit packet out at 92 bit IPG to clean buffer. If user disables this function then ADM6996L will transmit packet at 96 bit. 7 R/W Enable Trunk. 1: enable Port3 Trunk port. 0: disable. 14:8 ...
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... Ethernet Packet from Layer 2 Preamble/SFD Destination (6 bytes) Byte 0~5 4.3.9 VLAN Packet ADM6996L will check packet byte 12 &13. If byte[12:13]=8100h then this packet is a VLAN packet Tag Protocol TD 8100 Byte 12~13 Byte 14~15: Tag Control Information TCI Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID ...
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... ADM6996L 4.3.10 TOS IP Packet ADM6996L check byte 12 &13 if this value is 0800h then ADM6996L knows this is a TOP priority packet. Type 0800 Byte 12~13 IP header define Byte 14 Bit[7:0]: IP protocol version number & header length. Byte 15: Service type Bit[7~5]: IP Priority (Precedence ) from 7~0 Bit 4: No Delay (D) ...
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... R/W MAC Clone enable 0: Normal mode. Learning with SA only. ADM6996L fill/search MAC table only. 1: MAC Clone mode. Learning with SA, VID0. ADM6996L fill/search MAC table with VID0. This bit can let chip learn two same addresses with different VID0. ...
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... Port4 MAC MII Port Port0 Port1 4 100/10 LAN Port Below is new architecture by using ADM6996L serial chip VLAN function. The advantages of below are: 1. WAN Port can upgrade to 100/10 Full/Half , Auto MDIX. 2. WAN/LAN Port is programmable and put on same Switch need extra NIC and save lot of cost. ...
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... Traffic to CPU is Tag packet with VID=1. CPU can check VID to distinguish LAN traffic or WAN traffic. 2. WAN to CPU Traffic. ADM6996L WAN traffic to CPU only. Traffic to CPU is Tag packet with VID=2. CPU can check VID to distinguish LAN traffic or WAN traffic. 3. CPU to LAN Packet. ...
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... ADM6996L ADM6996L will check VLAN mapping setting first then check learning table. User does not worry LAN/WAN traffic mix up. Bit 10: Half Duplex Back Pressure enable. 1/enable, 0/disable. 4.3.13 Miscellaneous Configuration register, offset: 0x12h Bits Type Description 0 R/W Port0 MAC Lock. 1: Lock first MAC source address, 0: disable. ...
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... ADM6996L 4.3.16 Port0, 1 PVID bit Configuration Register, offset: 0x28h Bits Type Description 7:0 R/W Port0 PVID bit 11~4. These 8 bits combine with register 0x01h Bit [13~10] as full 12 bit VID. 15:8 RO Reserved 4.3.17 Port2, 3 PVID bit Configuration Register, offset: 0x29h Bits Type Description 7:0 R/W Port1 PVID bit 11~4. These 8 bits combine with register 0x03h Bit[13~10] as full 12 bit VID ...
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... R/W Control reserved MAC (0180C2000001) 1: Forward, 0: Discard. 15 R/W Control reserved MAC (0180C2000000) 1: Forward, 0: Discard. Note: Bit[10:8]: VLAN Tag shift register. ADM6996L will select 4 bit from total 12 bit VID as VLAN group reference. Bit[15:12]: IEEE 802.3 reserved DA forward or drop police. 4.3.21 Reserved Register, offset: 0x2dh Bits Type Description ...
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... ADM6996L Bits Type Description 11 R/W Reserved 12 R/W Port 4 LED Mode. 1:Link/Act/Speed 0:LinkAct/DupCol/Speed 15:13 R/W Reserved 4.3.25 Bandwidth Control Register0~3, offset: 0x31h Bits Type Description 2:0 R/W Port 0 Meter Threshold Control. Reference table below. 3 R/W Receive Packet Length Counted on the Source Port The switch will add length to the P0 counter. ...
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... EEPROM WRITE instruction only. If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate separated CS signal cycle for each Protection & WRITE instruction. CPU can directly program ADM6996L after 30ms of Reset signal rising edge with or without EEPROM Infineon-ADMtek Co. Ltd. ...
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... Reset signal is control by CPU with at least 100ms low. Point1 is Reset rising edge. CPU must prepare proper value on EECS(0), EESK, EDI, EDO(1) before this rising edge. ADM6996L will read this value into chip at Point2. CPU must keep these values over point2. Point2 is 200ns after Reset rising edge. ...
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... ADM6996L 4.5 Serial Register Map Register 0x00h 0x01h 0x02h 0x03h 0x04h 0x05h 0x06h 0x07h 0x08h 0x09h 0x0ah 0x0bh 0x0ch 0x0dh 0x0eh 0x0fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h 0x18h 0x19h 0x1ah 0x1bh 0x1ch 0x1dh 0x1eh 0x1fh 0x20h 0x21h 0x22h 0x23h ...
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... ADM6996L Register 0x2ah 0x2bh 0x2ch 0x2dh 0x2eh 0x2fh 0x30h 0x31h 0x32h 0x33h 0x34h 0x35h 0x36h 0x37h 0x38h 0x39h 0x3ah 0x3bh 0x3ch 4.6 Serial Register Description 4.6.1 Chip Identifier Register, offset: 0x00h Bits Type Description 3:0 RO 0000 (Version number) 31:4 RO 0x0007101h 4.6.2 Port Status 0 Register, offset: 0x01h ...
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... ADM6996L Bits Type Description 5 RO Reserved 6 RO Reserved 7 RO Reserved 8 RO Port 1 Linkup Status: 1: Link is established. 0: Link is not established Port 1 Speed Status: 1: 100Mb Mb Port 1 Duplex Status 1: Full Duplex. 0: Half Duplex Port 1 Flow Control Enable 1: 802.3X on for full duplex or back pressure on for half duplex. ...
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... ADM6996L Bits Type Description 1: 802.3X on for full duplex or back pressure on for half duplex. 0: Flow Control Disable 28 RO Port 4 Linkup Status: 1: Link is established. 0: Link is not established Port 4 Speed Status: 1: 100Mb Mb Port 4 Duplex Status 1: Full Duplex. 0: Half Duplex Port 4 Flow Control Enable 1: 802 ...
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... ADM6996L Bits Type Description 7:6 RO Port 1 Cable Broken Length 8 RO Port 1 Cable Broken 10:9 RO Reserved 11 RO Reserved 3:12 RO Port 2 Cable Broken Length 14 RO Port 2 Cable Broken 16:15 RO Reserved 17 RO Reserved 19:18 RO Port 3 Cable Broken Length 20 RO Port 3 Cable Broken 22:21 RO Port 4 Cable Broken Length 23 RO Port 4 Cable Broken ...
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... ADM6996L Bits Type Description 3 RO Reserved 4 RO Overflow of Port 2 Transmit Packet Count 5 RO Reserved 6 RO Overflow of Port 3 Transmit Packet Count 7 RO Overflow of Port 4 Transmit Packet Count 8 RO Overflow of Port 5 Transmit Packet Count 9 RO Overflow of Port 0 Transmit Packet Byte Count 10 RO Reserved ...
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... Register +1, Register ( Register is even number). Register, Register-1(Register is Odd number). Example: Read Register 00h then ADM6996L will drive 0x01h & 0x00h. Read Register 03h then ADM6996L will drive 0x03h & 0x02h. Idle: EESK must send at least one clock at idle time. ...
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... ADM6996L Preamble: At least 32 continuous “1”. Start: 01(2 bits) Opcode bits, Reset command) Device Address: Chip physical address as PHYAS[1:0]. Reset_type: Reset counter by port number or by counter index. 1: Clear dedicate port’s all counters. 0: Clear dedicate counter. Port_number or counter index: User define clear port or counter. ...
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... TX/FX Interface 5.1.1 TP Interface TXP TXN ADM6995 RXP RXN Transformer requirement: . TX/RX rate 1:1 . TX/RX central tap connect together to VCCA2. User can change TX/RX pin for easy layout but do not change polarity. ADM6996L supports auto polarity on receiving side. 5.1.2 FX Interface TXP TXN ADM6995 RXP RXN Infineon-ADMtek Co. Ltd. 1:1 0.01U R1 49 ...
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... ADM6996L 5.2 DC Characteristics 5.2.1 Absolute Maximum Rating Symbol Parameter V Power Supply CC Vcca2 TX line driver Vccpll PLL voltage Vccik Digital core voltage V Input Voltage IN Vout Output Voltage TSTG Storage Temperature PD Power Dissipation ESD ESD Rating 5.2.2 Recommended Operating Conditions Symbol Parameter Vcc Power Supply Vcca2 ...
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... ADM6996L 5.3 AC Characteristics 5.3.1 Power On Reset RST* All Configuration Pins Symbol Parameter TRST RST Low Period TCONF Start of Idle Pulse Width 5.3.2 EEPROM Interface Timing 0us EECS EESK tEWDD EEDO EEDI Symbol Parameter TESK EESK Period TESKL EESK Low Period TESKH EESK High Period ...
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... ADM6996L 5.3.3 10Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising hold 5.3.4 10Base-TX MII Output Timing ...
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... ADM6996L 5.3.5 100Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising hold 5.3.6 100Base-TX MII Output Timing ...
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... ADM6996L Symbol Parameter tCKH MII_TXCLK High Period tTXOD MII_TXD, MII_TXEN to MII_TXCLK Rising Output Delay 5.3.7 GPSI(7-wire) Input Timing 0ns GPSI_RXCLK GPSI_RXD GPSI_CRS/COL Symbol Parameter TCK GPSI_RXCLK Period TCKL GPSI_RXCLK Low Period TCKH GPSI_RXCLK High Period TTXS GPSI_RXD, GPSI_CRS/COL to GPSI_RXCLK Rising Setup ...
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... ADM6996L Symbol Parameter TCK GPSI_TXCLK Period TCKL GPSI_TXCLK Low Period TCKH GPSI_TXCLK High Period TOD GPSI_TXCLK Rising to GPSI_TXEN/GPSI_TXD Output Delay Infineon-ADMtek Co. Ltd. Conditions Min Typical 100 Electrical Specification Max Units 5-7 ...
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... ADM6996L Chapter 6 Packaging 6.1 128 Pin PQFP Outside Dimension Infineon-ADMtek Co. Ltd. 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12.5 mm 0.5 mm Appendix 6-1 ...