ISPLSI3320-70LQ Lattice Semiconductor Corp., ISPLSI3320-70LQ Datasheet
ISPLSI3320-70LQ
Specifications of ISPLSI3320-70LQ
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ISPLSI3320-70LQ Summary of contents
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... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 3320 Functional Block Diagram Input Bus TOE Output Routing Pool (ORP I I/O 2 I/O 3 I I/O 6 I/O 7 I/O 8 ...
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Description (continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 160 I/O cells, each of which is ...
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Absolute Maximum Ratings Supply Voltage V ................................................................................ -0.5 to +7.0V cc Input Voltage Applied ..................................................................... -2 Off-State Output Voltage Applied .................................................. -2 Storage Temperature ............................................................................. -65 to 150°C Case Temp. with Power Applied ........................................................... -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load conditions (See Figure 2) TEST CONDITION A 470Ω ...
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External Switching Characteristics 5 TEST 2 PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 24 I/O Register Bypass iobp t 25 I/O Latch Delay iolat t 26 I/O Register Setup Time before Clock iosu t 27 I/O Register Hold Time after Clock ioh t ioco 28 ...
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Internal Timing Parameters 2 PARAMETER # Outputs t 47 Output Buffer Delay Output Buffer Delay, Slew Limited Adder obs t 49 I/O Cell OE to Output Enabled oen t 50 I/O Cell OE to Output Disabled odis ...
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Timing Model I/O Cell I/O Reg Bypass I/O Pin #24 (Input) Input Register D Q RST #53 # Reset Y3,4 #52 Y0,1,2 GOE0,1 TOE Derivations of su, h and co from the Product ...
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Power Consumption Power consumption in the ispLSI 3320 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3. Typical Device Power Consumption vs fmax I CC can ...
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Signal Descriptions Signal Name GOE0, GOE1 Global Output Enable input pins. I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array. TOE Test Output Enable pin – This pin tristates all I/O pins when ...
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Signal Locations Signal 208-Pin PQFP GOE0, GOE1 133, 134 TOE 30 RESET 28 Y0, Y1, Y2, Y3, Y4 132, 130, 129, 128, 127 BSCAN/ispEN 27 TDI/SDI 25 TCK/SCLK 24 TMS/MODE 23 TRST 29 TDO/SDO 185 GND 11, 26, 42, 53, ...
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I/O Locations Signal PQFP BGA Signal I C14 I A15 I B15 I C15 I D15 I A17 ...
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Pin Configuration ispLSI 3320 208-Pin PQFP (with Heat Spreader) Pinout Diagram 1 I/O 140 2 I/O 141 3 I/O 142 4 I/O 143 5 I/O 144 6 I/O 145 7 I/O 146 8 I/O 147 9 I/O 148 10 I/O ...
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Signal Configuration ispLSI 3320 320-Ball BGA Signal Diagram I/O I/O I/O I I/O I/O ...
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Part Number Description ispLSI 3320 Device Family Device Number Speed f 100 = 100 MHz max MHz max Ordering Information FAMILY fmax (MHz) tpd (ns) 100 100 ispLSI 70 70 Specifications ispLSI 3320 – – XXX ...