TS80C31X2 ATMEL Corporation, TS80C31X2 Datasheet

Page 1

... Description TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism ...

Page 2

... Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA (1) RD (1) WR AT/TS80C31X2 2 (1) (1) RAM EUART 128x8 C51 CORE IB-bus CPU Timer 0 INT Parallel I/O Ports & Ext. Bus Timer 1 Ctrl Port 0Port 1 Port 2 Port 3 (1) (1) (1) (1) (1): Alternate function of Port 3 4428E–8051–02/08 ...

Page 3

... SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • ...

Page 4

... XTAL1 20 21 VSS 44 P1.5 1 P1.6 2 P1.7 3 RST 4 P3.0/RxD 5 NIC* 6 P3.1/TxD 7 8 P3.2/INT0 P3.3/INT1 9 P3.4/T0 10 P3.5/ *NIC: No Internal Connection AT/TS80C31X2 4 VCC P1 P1 P1.7 9 EA/VPP RST 10 ALE/PROG P3.0/RxD 11 PSEN NIC* 12 P2.7 / A15 P3.1/TxD 13 P2 ...

Page 5

... PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. AT/TS80C31X2 Name And Function permits a power-on reset using SS CC ...

Page 6

... XTAL1 19 21 XTAL2 18 20 AT/TS80C31X2 External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier ...

Page 7

... Enhanced UART 6.1 X2 Feature The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Save power consumption while keeping same CPU power (oscillator power saving). ...

Page 8

... Clear to select 12 clock periods per machine cycle (STD mode, F Set to select 6 clock periods per machine cycle (X2 mode, F Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) AT/TS80C31X2 8 X2 Mode ...

Page 9

... The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection 0 DPS Clear to select DPTR0. Set to select DPTR1. Reset Value = XXXX XXX0 Not bit addressable 4428E–8051–02/08 DPTR1 DPTR0 DPH(83H) DPL(82H Description AT/TS80C31X2 External Data Memory DPS 9 ...

Page 10

... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. AT/TS80C31X2 10 AUXR1 EQU 0A2H ...

Page 11

... TS80C31X2 Serial I/O Port The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different ...

Page 12

... The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: The following is an example of how to use given addresses to address different slaves: Slave A: Slave B: AT/TS80C31X2 12 RXD ...

Page 13

... SADDR 0101 0110b SADEN 1111 1100b 1111 111Xb SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b AT/TS80C31X2 ...

Page 14

... Table 9-2. SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable AT/TS80C31X2 4428E–8051–02/08 ...

Page 15

... Reset Value = 0000 0000b Bit addressable 4428E–8051–02/ SM2 REN TB8 SM1 Mode Description Baud Rate 0 Shift Register F /12 (/ mode) XTAL 1 8-bit UART Variable 2 9-bit UART F / XTAL XTAL 3 9-bit UART Variable AT/TS80C31X2 2 1 RB8 TI /32 (/32, / mode ...

Page 16

... Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT/TS80C31X2 POF ...

Page 17

... Interrupt System The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Fig- ure 10-1. Figure 10-1. Interrupt Control System INT0 TF0 INT1 TF1 RI TI Individual Enable Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 10-2 ...

Page 18

... Table 10- Bit Number Reset Value = 0XX0 0000b Bit addressable AT/TS80C31X2 18 IE Register -- IE - Interrupt Enable Register (A8h Bit Mnemonic Enable All interrupt bit Clear to disable all interrupts. EA Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit ...

Page 19

... Refer to PT1H for priority level. External interrupt 1 Priority bit PX1 Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit PT0 Refer to PT0H for priority level. External interrupt 0 Priority bit PX0 Refer to PX0H for priority level. AT/TS80C31X2 PT1 PX1 PT0 Description 0 PX0 ...

Page 20

... Table 10- Bit Number Reset Value = XXX0 0000b Not bit addressable AT/TS80C31X2 20 IPH Register -- IPH - Interrupt Priority High Register (B7h PSH Bit Mnemonic Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...

Page 21

... In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol- lowing the instruction that put TS80C31X2 into power-down mode. 4428E–8051–02/08 AT/TS80C31X2 can be lowered to save further power ...

Page 22

... Mode Memory Idle External Power Down External AT/TS80C31X2 22 Power-down phase Oscillator restart phase NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. ...

Page 23

... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the cir- cuit Table 26. shows the status of the port pins during ONCE mode. ...

Page 24

... Reset Value = 00X1 0000b Not bit addressable AT/TS80C31X2 24 switch-on. A warm start reset occurs while V CC rises from 0 to its nominal voltage. The POF can be set or cleared by software allow- PCON Register -- PCON - Power Control Register (87h SMOD0 ...

Page 25

... Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. AT/TS80C31X2 SJMP Label (80 FE) 25 ...

Page 26

... Power Down Current Power Supply Current Maximum values, X1 under (7) mode: RESET I Power Supply Current Maximum values (7) mode: operating AT/TS80C31X2 ± 10 MHz ± 10 MHz Parameters in Standard Voltage Min Typ -0.5 0 ...

Page 27

... DC Parameters for Low Voltage Min -0.5 0 0 (6) ( under reset is measured with all output pins disconnected; XTAL1 driven with (see Figure 14-5.), AT/TS80C31X2 Typ Max Unit 0.25+0.3 Freq (MHz) @12MHz 3.9 mA @16MHz 5.1 Typ Max Unit 0.5 ...

Page 28

... Figure 14-1. I AT/TS80C31X2 0.5V; XTAL2 N.C RST = Port oscillator used.. 2. Idle I is measured with all output pins disconnected; XTAL1 driven with 0 0.5 V; XTAL2 N.C; Port 3.). 3. Power Down I is measured with all output pins disconnected XTAL2 NC. ...

Page 29

... CLOCK XTAL1 SIGNAL V SS Test Condition, Idle Mode RST EA (NC) XTAL2 XTAL1 V SS Test Condition, Power-Down Mode CC AT/TS80C31X2 All other pins are disconnected All other pins are disconnected. CC All other pins are disconnected. 29 ...

Page 30

... PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 14-3. Port 0 Port ALE / PSEN 100 Table 8-5., Table 8-8. and Table 8-11. give the description of each AC symbols. Table 14-6., Table 14-9. and Table 14-12. give for each range the AC parameter. AT/TS80C31X2 30 V -0.5V 0. 0.2V ...

Page 31

... Max frequency for derating formula regarding the speed grade -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode (Table 14-7.) T= 50ns 75ns LLIV External Program Memory Characteristics Parameter AT/TS80C31X2 33.3 33 ns): 31 ...

Page 32

... LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min PXIX T Max PXIZ T Max AVIV T Max PLAZ AT/TS80C31X2 32 AC Parameters for Fix Clock - mode standard mode 40 30 MHz MHz 60 MHz equiv. Min Max Min Max ...

Page 33

... RD Low to Address Float RLAZ High to ALE high WHLH 4428E–8051–02/ CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 External Data Memory Characteristics Parameter AT/TS80C31X2 T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 33 ...

Page 34

... AVDV T 50 100 LLWL T 75 AVWL T 10 QVWX T 160 QVWH T 15 WHQX T 0 RLAZ WHLH AT/TS80C31X2 34 AC Parameters for a Fix Clock - mode standard mode 40 30 MHz MHz 60 MHz equiv. Min Max Min Max 85 135 85 135 60 102 ...

Page 35

... LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 AT/TS80C31X2 -V -L Units ...

Page 36

... Speed 40 MHz Symbol Min Max T 300 XLXL T 200 QVHX T 30 XHQX T 0 XHDX T 117 XHDV AT/TS80C31X2 36 T LLDV T LLWL T RLDV T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge ...

Page 37

... XLXL T XHQX XHDX T XHDV VALID VALID VALID Parameter Oscillator Period High Time Low Time Rise Time Fall Time AT/TS80C31X2 - 133 133 133 VALID VALID ...

Page 38

... For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20mA. 14.5.9 Clock Waveforms Valid in normal clock mode mode XTAL2 signal must be changed to XTAL2 divided by two. AT/TS80C31X2 38 -0 0.7V CC 0.2V -0 ...

Page 39

... INDICATES DPH OR P2 SFR TO PCH DPL OR Rt DATA OUT INDICATES DPH OR P2 SFR TO PCH OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS RXD SAMPLED =25°C fully loaded) RD and WR propagation delays are A AT/TS80C31X2 STATE3 STATE4 STATE5 P1P2 P1P2 P1P2 PCL OUT DATA SAMPLE FLOAT ...

Page 40

... Part Number Memory Size TS80C31X2-MCA TS80C31X2-MCB TS80C31X2-MCC TS80C31X2-MCE TS80C31X2-LCA TS80C31X2-LCB TS80C31X2-LCC TS80C31X2-LCE TS80C31X2-VCA TS80C31X2-VCB TS80C31X2-VCC TS80C31X2-VCE TS80C31X2-MIA TS80C31X2-MIB TS80C31X2-MIC TS80C31X2-MIE TS80C31X2-LIA TS80C31X2-LIB TS80C31X2-LIC TS80C31X2-LIE TS80C31X2-VIA TS80C31X2-VIB TS80C31X2-VIC TS80C31X2-VIE AT80C31X2-3CSUM ROMLess AT80C31X2-SLSUM ROMLess AT80C31X2-RLTUM ROMLess AT80C31X2-3CSUL ROMLess AT80C31X2-SLSUL ROMLess AT80C31X2-RLTUL ROMLess AT/TS80C31X2 ...

Page 41

... Tape and Reel available for SL, PQFP and RL packages MHz in X2 Mode. 4428E–8051–02/08 Temperature Supply Voltage Range Max Frequency 5V ±10% Industrial & Green 5V ±10% Industrial & Green 5V ±10% Industrial & Green AT/TS80C31X2 Package Packing (3) 60 MHz PDIL40 Stick (3) 60 MHz PLCC44 Stick (3) 60 MHz ...

Page 42

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © Atmel Corporation 2008. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...