MC68340 Freescale Semiconductor, Inc, MC68340 Datasheet
MC68340
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MC68340 Summary of contents
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... Freescale Semiconductor, Inc. µ MOTOROLA Integrated Processor with DMA ©MOTOROLA INC., 1992 For More Information On This Product, MC68340 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others ...
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... The MC68340 Integrated with DMA Processor User’s Manual describes the programming, capabilities, registers, and operation of the MC68340; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68340; and the MC68340 Integrated Processor with DMA Product Brief provides a brief description of the MC68340 capabilities. This user’s manual is organized as follows: ...
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... Data Bus (D15–D0).......................................................................................... 2-4 2.4 Function Codes (FC3–FC0)............................................................................ 2-5 Chip Selects ( CS3 – CS0 ) ................................................................................ 2-5 2.5 2.6 Interrupt Request Level ( IRQ7 , IRQ6 , IRQ5 , IRQ3 ) ................................... 2-6 MOTOROLA For More Information On This Product, Title Section 1 Device Overview Section 2 Signal Descriptions MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number iii ...
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... Clear to Send ( CTSA , CTSB )..................................................................... 2-11 Request to Send ( RTSA , RTSB )................................................................ 2-11 2.13.6 Transmitter Ready ( T RDYA )..................................................................... 2-11 2.13.7 2.13.8 Receiver Ready ( R RDYA ) ......................................................................... 2-12 2.14 Timer Signals .................................................................................................... 2-12 Timer Gate ( TGATE2 , TGATE1 )................................................................ 2-12 2.14.1 2.14.2 Timer Input (TIN2, TIN1) .............................................................................. 2-12 2.14.3 Timer Output (TOUT2, TOUT1)................................................................... 2-12 iv For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... Long-Word Operand to 16-Bit Port, Aligned........................................ 3-12 3.2.4 Bus Operation................................................................................................ 3-14 Synchronous Operation with DSACK ..................................................... 3-14 3.2.5 3.2.6 Fast Termination Cycles.............................................................................. 3-15 3.3 Data Transfer Cycles........................................................................................ 3-16 3.3.1 Read Cycle..................................................................................................... 3-16 3.3.2 Write Cycle..................................................................................................... 3-18 3.3.3 Read-Modify-Write Cycle............................................................................. 3-19 MOTOROLA For More Information On This Product, Title ).......................................................................... 2-13 CCSYN and GND)................................................ 2-13 CC Section 3 Bus Operation MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number v ...
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... Using the Periodic Timer as a Real-Time Clock ............................. 4-9 4.2.2.7 Simultaneous Interrupts by Sources in the SIM40............................. 4-9 4.2.3 Clock Synthesizer Operation...................................................................... 4-9 4.2.3.1 Phase Comparator and Filter ................................................................. 4-11 4.2.3.2 Frequency Divider .................................................................................... 4-12 4.2.3.3 Clock Control............................................................................................. 4-13 4.2.4 Chip Select Operation ................................................................................. 4-13 4.2.4.1 Programmable Features.......................................................................... 4-14 vi For More Information On This Product, Title Section 4 MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... Port A Pin Assignment Register 2 (PPARA2)....................................... 4-34 4.3.5.3 Port A Data Direction Register (DDRA)................................................. 4-34 4.3.5.4 Port A Data Register (PORTA)................................................................ 4-34 4.3.5.5 Port B Pin Assignment Register (PPARB) ............................................ 4-35 4.3.5.6 Port B Data Direction Register (DDRB)................................................. 4-35 4.3.5.7 Port B Data Register (PORTB, PORTB1) .............................................. 4-35 4.4 MC68340 Initialization Sequence................................................................. 4-36 4.4.1 Startup ............................................................................................................ 4-36 4.4.2 SIM40 Module Configuration ..................................................................... 4-36 4.4.3 SIM40 Example Configuration Code........................................................ 4-38 5.1 Overview............................................................................................................. 5-1 5.1.1 Features.......................................................................................................... 5-2 5.1.2 Virtual Memory ...
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... Table Example 5: Surface Interpolations............................................. 5-36 5.3.5 Nested Subroutine Calls............................................................................. 5-36 5.3.6 Pipeline Synchronization with the NOP Instruction................................ 5-36 5.4 Processing States............................................................................................. 5-36 5.4.1 State Transitions........................................................................................... 5-37 5.4.2 Privilege Levels............................................................................................. 5-37 5.4.2.1 Supervisor Privilege Level...................................................................... 5-37 5.4.2.2 User Privilege Level................................................................................. 5-39 viii For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... Four-Word Stack Frame .......................................................................... 5-60 5.5.4.2 Six-Word Stack Frame............................................................................. 5-60 5.5.4.3 Bus Error Stack Frame............................................................................. 5-60 5.6 Development Support...................................................................................... 5-63 5.6.1 CPU32 Integrated Development Support................................................ 5-63 5.6.1.1 Background Debug Mode (BDM) Overview ........................................ 5-64 5.6.1.2 Deterministic Opcode Tracking Overview............................................ 5-64 MOTOROLA For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number ix ...
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... No Operation (NOP)............................................................................. 5-85 5.6.2.8.16 Future Commands................................................................................ 5-86 5.6.3 Deterministic Opcode Tracking.................................................................. 5-86 Instruction Fetch ( IFETCH )...................................................................... 5-86 5.6.3.1 Instruction Pipe ( IPIPE )........................................................................... 5-87 5.6.3.2 5.6.3.3 Opcode Tracking during Loop Mode .................................................... 5-88 5.7 Instruction Execution Timing........................................................................... 5-88 5.7.1 Resource Scheduling .................................................................................. 5-88 5.7.1.1 Microsequencer ........................................................................................ 5-89 5.7.1.2 Instruction Pipeline................................................................................... 5-89 x For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... DMA Done ( DONE )..................................................................................... 6-4 6.3 Transfer Request Generation ......................................................................... 6-4 6.3.1 Internal Request Generation....................................................................... 6-4 6.3.1.1 Internal Request, Maximum Rate........................................................... 6-5 6.3.1.2 Internal Request, Limited Rate ............................................................... 6-5 6.3.2 External Request Generation ..................................................................... 6-5 6.3.2.1 External Burst Mode................................................................................. 6-5 MOTOROLA For More Information On This Product, Title Section 6 DMA Controller Module MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xi ...
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... DMA Channel Example Configuration Code .......................................... 6-38 7.1 Module Overview.............................................................................................. 7-2 7.1.1 Serial Communication Channels A and B............................................... 7-3 7.1.2 Baud Rate Generator Logic ........................................................................ 7-3 7.1.3 Internal Channel Control Logic.................................................................. 7-3 7.1.4 Interrupt Control Logic ................................................................................. 7-3 xii For More Information On This Product, Title Section 7 Serial Module MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... Remote Loopback Mode ......................................................................... 7-14 7.3.4 Multidrop Mode ............................................................................................. 7-15 7.3.5 Bus Operation................................................................................................ 7-17 7.3.5.1 Read Cycles............................................................................................... 7-17 7.3.5.2 Write Cycles............................................................................................... 7-17 7.3.5.3 Interrupt Acknowledge Cycles................................................................ 7-17 7.4 Register Description and Programming ....................................................... 7-17 7.4.1 Register Description..................................................................................... 7-17 7.4.1.1 Module Configuration Register (MCR).................................................. 7-19 MOTOROLA For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xiii ...
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... Timer Modules Signal Definitions ................................................................. 8-4 8.2.1 Timer Input (TIN1, TIN2) .............................................................................. 8-5 Timer Gate ( TGATE1 , TGATE2 )................................................................ 8-6 8.2.2 8.2.3 Timer Output (TOUT1, TOUT2)................................................................... 8-6 8.3 Operating Modes .............................................................................................. 8-6 8.3.1 Input Capture/Output Compare.................................................................. 8-6 8.3.2 Square-Wave Generator............................................................................. 8-8 xiv For More Information On This Product, Title Section 8 Timer Modules MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... Boundary Scan Register ................................................................................. 9-3 9.4 Instruction Register........................................................................................... 9-9 9.4.1 EXTEST (000) ............................................................................................... 9-10 9.4.2 SAMPLE/PRELOAD (001) .......................................................................... 9-10 9.4.3 BYPASS (X1X, 101)..................................................................................... 9-11 9.4.4 HI-Z (100) ....................................................................................................... 9-11 9.5 MC68340 Restrictions...................................................................................... 9-11 9.6 Non-IEEE 1149.1 Operation........................................................................... 9-12 10.1 Minimum System Configuration................................................................... 10-1 10.1.1 Processor Clock Circuitry.......................................................................... 10-1 MOTOROLA For More Information On This Product, Title Section 9 Section 10 Applications MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xv ...
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... Memory Interface Information....................................................................... 10-5 10.2.1 Using an 8-Bit Boot ROM........................................................................... 10-5 10.2.2 Access Time Calculations......................................................................... 10-6 10.2.3 Calculating Frequency-Adjusted Output ................................................ 10-7 10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode.................................................................. 10-10 10.3 Power Consumption Considerations.......................................................... 10-10 10.3.1 MC68340 Power Reduction at 5V .......................................................... 10-11 10.3.2 MC68340V (3.3 V) ..................................................................................... 10-13 11.1 Maximum Rating ............................................................................................. 11-1 11.2 Thermal Characteristics................................................................................. 11-1 11.3 Power Considerations ................................................................................... 11-2 11.4 AC Electrical Specification Definitions ....................................................... 11-2 11.5 DC Electrical Specifications ......................................................................... 11-5 11 ...
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... Figure Number 1-1 Block Diagram......................................................................................................... 1-1 2-1 Functional Signal Groups ..................................................................................... 2-1 3-1 Input Sample Window............................................................................................ 3-2 3-2 MC68340 Interface to Various Port Sizes.......................................................... 3-7 3-3 Long-Word Operand Read Timing from 8-Bit Port............................................ 3-11 3-4 Long-Word Operand Write Timing to 8-Bit Port................................................. 3-12 3-5 Long-Word and Word Read and Write Timing—16-Bit Port ........................... 3-13 3-6 Fast Termination Timing........................................................................................ 3-15 3-7 Word Read Cycle Flowchart ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 4-5 MC68340 Crystal Oscillator.................................................................................. 4-10 4-6 Clock Block Diagram for External Oscillator Operation................................... 4-11 4-7 Full Interrupt Request Multiplexer........................................................................ 4-16 4-8 SIM40 Programming Model.................................................................................. 4-19 5-1 CPU32 Block Diagram........................................................................................... 5-3 5-2 Loop Mode Instruction Sequence ....................................................................... 5-3 5-3 User Programming Model..................................................................................... 5-9 5-4 Supervisor Programming Model Supplement .................................................. 5-9 5-5 Status Register ...
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... Variable-Width Single-Shot Pulse Generator Mode........................................ 8-11 8-8 Pulse-Width Measurement Mode ........................................................................ 8-12 8-9 Period Measurement Mode .................................................................................. 8-14 8-10 Event Count Mode.................................................................................................. 8-15 8-11 Timer Module Programming Model..................................................................... 8-18 9-1 Test Access Port Block Diagram.......................................................................... 9-2 9-2 TAP Controller State Machine.............................................................................. 9-3 MOTOROLA For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xix ...
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... Signal Width Specifications................................................................................ 10-8 10-13 Skew between Two Outputs............................................................................... 10-9 10-14 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode.............................................................................. 10-10 10-15 MC68340 Current vs. Activity at 5 V.................................................................. 10-11 10-16 MC68340 Current vs. Voltage/Temperature.................................................... 10-12 10-17 MC68340 Current vs. Clock Frequency at 5 V................................................ 10-12 11-1 Drive Levels and Test Points for AC Specifications....................................... 11-4 11-2 Read Cycle Timing Diagram............................................................................... 11-11 11-3 Write Cycle Timing Diagram............................................................................... 11-12 11-4 Fast Termination Read Cycle Timing Diagram ...
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... Serial Module Asynchronous Mode Timing (SCLK–16X)............................ 11-23 11-18 Serial Module Synchronous Mode Timing Diagram ..................................... 11-23 11-19 Test Clock Input Timing Diagram....................................................................... 11-25 11-20 Boundary Scan Timing Diagram ....................................................................... 11-26 11-21 Test Access Port Timing Diagram...................................................................... 11-26 MOTOROLA For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xxi ...
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... Shift and Rotate Operations.................................................................................. 5-25 5-8 Bit Manipulation Operations ................................................................................. 5-25 5-9 Binary-Coded Decimal Operations ..................................................................... 5-26 5-10 Program Control Operations................................................................................. 5-26 5-11 System Control Operations................................................................................... 5-28 5-12 Condition Tests ....................................................................................................... 5-29 5-13 Standard Usage Entries........................................................................................ 5-30 5-14 Compressed Table Entries ................................................................................... 5-32 xxii For More Information On This Product, LIST OF TABLES Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev.1 Number MOTOROLA ...
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... IEx Encoding............................................................................................................ 8-21 8-4 POTx Encoding ....................................................................................................... 8-22 8-5 MODEx Encoding ................................................................................................... 8-22 8-6 OCx Encoding ......................................................................................................... 8-22 9-1 Boundary Scan Control Bits ................................................................................. 9-4 9-2 Boundary Scan Bit Definitions ............................................................................. 9-5 9-3 Instructions............................................................................................................... 9-10 10-1 Memory Access Times at 16.78 MHz................................................................ 10-7 10-2 Typical Electrical Characteristics....................................................................... 10-13 MOTOROLA For More Information On This Product, Title MC68340 USER'S MANUAL Go to: www.freescale.com UM Rev Number xxiii ...
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... The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing. Systems requiring very high-speed block transfers of data can especially benefit from the MC68340 ...
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... M68300 FAMILY The MC68340 is one of a series of components in the M68300 family. Other members of the family include the MC68302, MC68330, MC68331, MC68332, and MC68333. 1-2 For More Information On This Product, — ...
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... CENTRAL PROCESSOR UNIT The CPU32 is a powerful central processor that supervises system functions, makes decisions, manipulates data, and directs I/O. A special debugging mode simplifies processor emulation during system debug. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 1- 3 ...
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... Position-independent code is easily written. The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most instructions execute in one-half the number of clocks compared to the original MC68000, yielding an overall 1.6 times the performance of the same-speed MC68000 and measuring 10,045 Dhrystones/sec 25 ...
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... To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller, a serial module, and two timers. The processor communicates with these modules over the on-chip intermodule bus (IMB). ...
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... SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. System configuration and various monitors and timers are provided in the MC68340. Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system does not lock up when there is no response to a memory access. The bus fault monitor can reset the processor when a catastrophic bus failure occurs ...
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... Freescale Semiconductor, Inc. 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). 1.3.2 Direct Memory Access Module ...
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... The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple timer in the SIM40. These general-purpose counter/timers can be used for precisely timed events without the errors to which software-based counters and timers are susceptible— ...
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... SIM40's periodic interrupt timer. 1.5 PHYSICAL The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz +70 C and - +85 C, and 5 and 3.3 V 0.3 supply voltages (reduced frequencies at 3.3 V) Thirty-two power and ground leads minimize ground bounce and ensure proper isolation of different sections of the chip, including the clock oscillator ...
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... Freescale Semiconductor, Inc. 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number BR1114/D MC68340/D MC68340UM/AD M68000PM/AD AN1063/D AN453 BR573/D BR729/D BR1407/D 1-10 For More Information On This Product, Document Name M68300 Integrated Processor Family MC68340 Technical Summary MC68340 User's Manual ...
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... Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1. A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 PORT A A27/PORT A3/IACK3 A26/PORT A2/IACK2 A25/PORT A1/IACK1 A24/PORT A0 A23–A0 D15–D0 FC3– ...
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... Freescale Semiconductor, Inc. 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics ...
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... Provides a clock for IEEE 1149.1 test logic Controls test mode operations Shifts in instructions and test data Shifts out instructions and test data Quiet power supply to VCO; also used to control synthesizer mode after reset. Power supply and ground to the MC68340 MC68340 USER’S MANUAL Go to: www.freescale.com Input/ Output In/I/O ...
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... DATA BUS (D15–D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the ...
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... For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. ...
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... MC68340 and external devices as listed in Table 2-3. During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate ...
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... Freescale Semiconductor, Inc. 2.7.3 Data Strobe ( output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle ...
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... Reset ( RESET ) This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM40) resets the MC68340 and all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices; the internal state of the CPU32 is not affected. The on-chip modules are reset, except for the SIM40 ...
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... DSI This development serial input signal helps to provide serial communications for background debug mode. 2.11.2 Instruction Pipe (IPIPE) This pin functions as IPIPE in normal operation and as DSO in background debug mode. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 2- 9 ...
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... DMA bus cycle to indicate that the last data transfer is being performed. DONE is an active input in any mode output only active in external request mode. An external pullup resistor is required even during operation in the internal request mode. 2-10 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... When used for this function, these outputs are controlled by the value of bit 1 and bit 0, respectively, in the output port data registers. 2.13.7 Transmitter Ready (T RDYA) This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 2- 11 ...
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... Timer Input (TIN2, TIN1) These inputs can be programmed as clocks that cause events to occur in the counters and prescalers. 2.14.3 Timer Output (TOUT2, TOUT1) These outputs drive the various output waveforms generated by the timers. 2-12 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Integration Module for more information. 2.17 SYSTEM POWER AND GROUND (V CC AND GND) These pins provide system power and ground to the MC68340. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. ...
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... Out EXTAL, XTAL In, Out XFC In MODCK In/I/O IFETCH /DSI Out/In IPIPE /DSO Out/Out BKPT /DSCLK In/In FREEZE Out RxDA, RxDB In MC68340 USER’S MANUAL Go to: www.freescale.com Active State Three-State — Yes —/—/Low Yes — Yes — Yes Low/Low/— No Low/Low No Low — ...
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... DONE2, DONE1 I/O TGATE2, In TGATE1 TIN2, TIN1 In TOUT2, TOUT1 Out TCK In TMS In TDI In TDO Out V CCSYN – GND – MC68340 USER’S MANUAL Go to: www.freescale.com Three-State — No Low — Low/— No — — Low/— Low — Low No Low No Low — ...
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... External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data ...
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... Bus Control Signals The MC68340 initiates a bus cycle by driving the A31–A0, SIZx, FCx, and R/ W outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3–FC0. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) ...
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... Long Word Address Spaces Reserved (Motorola User Data Space User Program Space Reserved (User ) Reserved (Motorola Supervisor Data Space Supervisor Program Space CPU Space DMA Space MC68340 USER’S MANUAL Go to: www.freescale.com 3- 3 ...
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... Data Bus (D15–D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle ...
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... During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACK inputs. Refer to Table 3-3 for DSACK encoding. ...
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... Freescale Semiconductor, Inc. For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation) ...
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... Section 5 CPU32 for more information on exception processing. 3.2.3 Operand Transfer Cases The following cases are examples of the allowable alignments of operands to ports. 3.2.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single- byte operand. ...
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... DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 15–8 and ignores bits 7–0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the operand from bits 15– ...
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... For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15–8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port ...
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... MC68340 reads the data on the data bus and terminates the cycle. For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the entire operand from bits 15–0 of the data bus and asserts DSACK1 to terminate the bus cycle ...
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... Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA For More Information On This Product BYTES 2 BYTES OP1 BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS MC68340 USER’S MANUAL Go to: www.freescale.com BYTE OP3 OP2 BYTE READ 3- 11 ...
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... OP1 OP2 (OP1) (OP3) WRITE WRITE LONG-WORD OPERAND WRITE TO 8-BIT BUS OP1 OP2 OP3 SIZ1 SIZ0 OP1 0 0 OP3 1 0 MC68340 USER’S MANUAL Go to: www.freescale.com BYTE OP3 (OP3) WRITE A0 DSACK1 DSACK0 MOTOROLA ...
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... FROM 16-BIT BUS Figure 3-5. Long-Word and Word Read and Write Timing—16-Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15– ...
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... If the assertion of DSACK is recognized on a particular falling edge of the clock, valid data is latched into the MC68340 (for a read cycle) on the next falling clock edge if the data meets the data setup time. In this case, the parameter for asynchronous operation can be ignored ...
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... DSACK , BERR (and HALT ) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK is recognized. This setup time is critical, and the MC68340 may exhibit erratic behavior violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS ...
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... During a read cycle, the MC68340 receives data from a memory or peripheral device. If the instruction specifies a long-word or word operation, the MC68340 attempts to read two bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal A0, and the port size ...
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... To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. ...
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... S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15– ...
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... Freescale Semiconductor, Inc. State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems SIZ1/SIZ0, and FC3– FC0 also remain valid throughout S5. The external device must keep DSACK asserted until it detects the negation (whichever it detects first) ...
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... S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S2. State 0—The MC68340 drives R/ W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S0. State 1—In S1, the MC68340 asserts AS , indicating a valid address on the address bus. ...
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... DSACK when it has successfully stored the data. State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems and FC3–FC0 also remain valid throughout S5. If more than one write cycle is required, states S0– ...
Page 71
... A4–A2 (BKPT#7), and the T-bit (A1) is set. If this bus cycle is terminated by BERR , the MC68340 performs hardware breakpoint exception processing. If this bus cycle is terminated by DSACK , the MC68340 ignores data on the data bus and continues execution of the next instruction. ...
Page 72
... The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the MC68340 is going into LPSTOP mode external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT ...
Page 73
... For More Information On This Product, IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE REPLACEMENT OPCODE ON DATA BUS 2. ASSERT DSACKx 1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1. ASSERT DSACKx 1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING (B) 1. NEGATE DSACKx or BERR MC68340 USER’S MANUAL Go to: www.freescale.com EXTERNAL DEVICE -OR- -OR- MOTOROLA ...
Page 74
... Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned) MOTOROLA For More Information On This Product BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ INSTRUCTION WORD FETCH MC68340 USER’S MANUAL Go to: www.freescale.com CPU SPACE FETCHED INSTRUCTION EXECUTION BREAKPOINT ACKNOWLEDGE 3- 25 ...
Page 75
... Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 3-26 For More Information On This Product BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ BUS ERROR ASSERTED MC68340 USER’S MANUAL Go to: www.freescale.com CPU SPACE EXCEPTION STACKING BREAKPOINT ACKNOWLEDGE MOTOROLA ...
Page 76
... The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.4.4.2 Autovector Interrupt Acknowledge Cycle. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 3- 27 ...
Page 77
... TYPE FIELD (A19–A16 SET R/W TO READ 5. SET FC3–FC0 TO 0111 6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE TRANSFER 7. ASSERT AS AND DS 8. ASSERT THE CORRESPONDING IACKx STROBE. ACQUIRE VECTOR NUMBER 1. LATCH VECTOR NUMBER 2. NEGATE DS AND AS START NEXT CYCLE MC68340 USER’S MANUAL Go to: www.freescale.com MC68340 MOTOROLA ...
Page 78
... AVEC , the DSACK signals and MOTOROLA For More Information On This Product, 0–2 CLOCKS INTERRUPT LEVEL CPU SPACE 1 BYTE VECTOR FROM 16-BIT PORT VECTOR FROM 8-BIT PORT INTERNAL ARBITRATION IACK CYCLE MC68340 USER’S MANUAL Go to: www.freescale.com S0 S2 WRITE STACK signals are asserted 3- 29 ...
Page 79
... The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)). ...
Page 80
... READ * Internal Arbitration may take between 0–2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA For More Information On This Product 0–2 CLOCKS* INTERRUPT LEVEL CPU SPACE 1 BYTE INTERNAL ARBITRATION IACK CYCLE MC68340 USER’S MANUAL Go to: www.freescale.com WRITE STACK 3- 31 ...
Page 81
... MC68340 clock. This assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68340 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used ...
Page 82
... EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5 data is valid, assert DSACK (case 1). 2. Delay DSACK until data is verified and assert BERR with or without DSACK if data is in error (case 3) ...
Page 83
... DSACK is recognized. If BERR is not stable at this time, the MC68340 may exhibit erratic behavior. BERR has priority over DSACK . In this case, data may be present on the bus, but it may not be valid ...
Page 84
... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D0 BERR READ CYCLE WITH BUS Figure 3-17. Bus Error without DSACK MOTOROLA For More Information On This Product INTERNAL ERROR PROCESSING MC68340 USER’S MANUAL Go to: www.freescale.com STACK WRITE 3- 35 ...
Page 85
... Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20). The MC68340 terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic ...
Page 86
... The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the bus during a read-modify-write operation. Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR and BR ( HALT must not be included) ...
Page 87
... A31–A0, FCx, SIZx, and R/ W signals remain in the same state. The halt operation has no effect on bus arbitration (see 3.6 Bus Arbitration). When bus arbitration occurs while the MC68340 is halted, the address and control signals are also placed in the high- impedance state. Once bus mastership is returned to the MC68340, if HALT is still ...
Page 88
... Freescale Semiconductor, Inc. asserted, the A31–A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D10 HALT BR BG BGACK READ 3 ...
Page 89
... The bus design of the MC68340 provides for a single bus master at any one time, either the MC68340 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68340 internal bus. Bus arbitration is the protocol by which an external device becomes bus master ...
Page 90
... ORed to the MC68340. In such a system, more than one bus request could be asserted simultaneously negated a few clock cycles after the transition of BGACK . However, if bus requests are still pending after the negation the MC68340 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus ...
Page 91
... BGACK Figure 3-23. Bus Arbitration Timing Diagram—Idle Bus Case CLKOUT A31–A0 D15– R/W DSACK0, DSACK1 BR BG BGACK Figure 3-24. Bus Arbitration Timing Diagram—Active Bus Case 3-42 For More Information On This Product MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 92
... SIZx and DSACK ). • During an external operand transfer, the MC68340 does not assert BG as long as RMC is asserted. • If the show cycle bits SHEN1–SHEN0 = 01, the MC68340 does not assert external master. Externally, the BG signal can be routed through a daisy-chained network or a priority- encoded network ...
Page 93
... MC68340. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68340 is bus master. R and A keep the arbiter in state 0 as long as they are both negated. The MC68340 does not allow arbitration of the external bus during the RMC sequence. ...
Page 94
... MOTOROLA For More Information On This Product STATE STATE STATE BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL MC68340 USER’S MANUAL Go to: www.freescale.com STATE ...
Page 95
... BKPT Figure 3-26. Show Cycle Timing Diagram 3.7 RESET OPERATION The MC68340 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines: 1. EXTRST (external reset) drives the external RESET pin. ...
Page 96
... Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the MC68340 causes any bus cycle in progress to terminate as if DSACK or BERR had been asserted. In addition, the MC68340 appropriately initializes registers for a reset exception. Asynchronous reset sources include power-up, software watchdog, double bus fault resets, and execution of the RESET instruction ...
Page 97
... First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles. The SIM40 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset ...
Page 98
... Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities. The SIM40 includes the following functions: • ...
Page 99
... CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. The device signals its port size and indicates completion of the bus cycle through the use of the DSACK inputs ...
Page 100
... SIM40. All M68000 family members are designed to provide maximum system safeguards extension of the family, the MC68340 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided by external circuits are incorporated in this device ...
Page 101
... The SIM40 provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 s to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function. 4-4 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 102
... MOTOROLA For More Information On This Product, MODULE CONFIGURATION RESET STATUS DOUBLE BUS FAULT MONITOR BUS MONITOR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG 9 2 PERIODIC INTERRUPT TIMER MC68340 USER’S MANUAL Go to: www.freescale.com HALT RESET REQUEST BERR SOFTWARE RESET REQUEST or IRQ7 IRQ7-IRQ1 4- 5 ...
Page 103
... The bus monitor feature cannot be disabled for internal accesses to an internal module. The internal bus monitor cannot check the DSACK response on the external bus unless the MC68340 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles ...
Page 104
... MOTOROLA For More Information On This Product, PITCLK . . 4 CLOCK MUX 9 PRECLK SWCLK 15 STAGE DIVIDER CHAIN ( 512) is divided by 4 before driving the modulus MC68340 USER’S MANUAL Go to: www.freescale.com PITR PIT MODULUS COUNTER INTERRUPT RESET ...
Page 105
... For More Information On This Product, PITR count value = EXTAL frequency/prescaler value PITR count value = = PITR count value PITR count value = 32768/512 = PITR count value = PITR (122 s) = PITR (62.5 ms) MC68340 USER’S MANUAL Go to: www.freescale.com 2 2 32768 8192 MOTOROLA ...
Page 106
... Section 11 Electrical Characteristics. When MOTOROLA For More Information On This Product, = (PIT period) (EXTAL frequency) (Prescaler value (1) (32768) (512 (decimal) Description MC68340 USER’S MANUAL Go to: www.freescale.com MODCK V CCSYN Reset Operating Value Value ...
Page 107
... DIVIDER 6 Y NOTE 1: Must be low-leakage capacitor. Figure 4-4. Clock Block Diagram for Crystal Operation Figure 4-5. MC68340 Crystal Oscillator A separate power pin (V CCSYN the device powered down and to provide increased noise immunity for the clock circuits. The source for V should be a quiet power supply with adequate external bypass ...
Page 108
... The result of MOTOROLA For More Information On This Product, V CCSYN 1 XFC V CCSYN XFC PIN LOW-PASS FILTER FEEDBACK DIVIDER CLOCK CONTROL should be connected to a quiet 5-V source. CCSYN MC68340 USER’S MANUAL Go to: www.freescale.com 0.1 µF .01 µF VCO CLKOUT SYSTEM CLOCK 4- 11 ...
Page 109
... VCO frequency limits are given in Section 11 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz. 4-12 For More Information On This Product, pins. The XFC capacitor should CCSYN (2+2W+ (Y+1) CRYSTAL (2– VCO SYSTEM MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 110
... Chip Select Operation Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. The MC68340 integrates these functions on chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip select function contains register pairs for each external chip select signal. The pair consists of a base address register and an address mask register that define the characteristics of a single chip select ...
Page 111
... When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register. 4-14 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 112
... For More Information On This Product, NOTE Pin Function PPARA1 = 0 PPARA1 = 1 PPARA1 = 0 PPARA2 = 0 PPARA2 = X PPARA2 = 1 A31 PORT A7 A30 PORT A6 A29 PORT A5 A28 PORT A4 A27 PORT A3 A26 PORT A2 A25 PORT A1 A24 PORT A0 MC68340 USER’S MANUAL Go to: www.freescale.com IACK7 IACK6 IACK5 IACK4 IACK3 IACK2 IACK1 — ...
Page 113
... Pin Function FIRQ = 0 FIRQ = 1 PPARB = 1 PPARB = 0 IRQ7 PORTB7 IRQ6 PORTB6 IRQ5 PORTB5 IRQ3 PORTB3 CS3 PORTB4 CS2 PORTB2 CS1 PORTB1 CS0 AVEC MODCK PORTB0 MC68340 USER’S MANUAL Go to: www.freescale.com FIRQ = 1 PPARB = 1 IRQ7 IRQ6 IRQ5 IRQ3 IRQ4 IRQ2 IRQ1 AVEC MODCK MOTOROLA ...
Page 114
... Low-Power Stop Executing the LPSTOP instruction provides reduced power consumption when the MC68340 is idle; only the SIM40 remains active. Operation of the SIM40 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see Table 4-3). LPSTOP disables the clock to the software watchdog in the low state. The software watchdog remains stopped until the LPSTOP mode ends ...
Page 115
... The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. A CPU32 RESET instruction will not affect any of the SIM40 registers. 4-18 For More Information On This Product, NOTE: MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 116
... BASE ADDRESS 1 CS1 BASE ADDRESS 2 CS1 ADDRESS MASK 1 CS2 ADDRESS MASK 2 CS2 BASE ADDRESS 1 CS2 BASE ADDRESS 2 CS2 ADDRESS MASK 1 CS3 ADDRESS MASK 2 CS3 BASE ADDRESS 1 CS3 BASE ADDRESS 2 CS3 MC68340 USER’S MANUAL Go to: www.freescale.com 0 SYSTEM PROTECTION CLOCK SYSTEM PROTECTION EBI EBI ...
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... MC68340 USER’S MANUAL Go to: www.freescale.com $0003FF00 ...
Page 118
... D0 with the value to be written into MBAR write the value contained in D0 into MBAR SHEN1 SHEN0 SUPV MC68340 USER’S MANUAL Go to: www.freescale.com $000 IARB3 IARB2 IARB1 IARB0 Supervisor Only ...
Page 119
... IARB field to a value from $F (highest priority (lowest priority). A 4-22 For More Information On This Product, ACTION Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 120
... Bits 3, 0—Reserved MOTOROLA For More Information On This Product AV6 AV5 AV4 AV3 AV2 AV1 Supervisor Only NOTE POW SW DBF 0 LOC SYS Supervisor Only MC68340 USER’S MANUAL Go to: www.freescale.com $006 $007 ...
Page 121
... For More Information On This Product SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 Supervisor Only SWRI SWT1 SWT0 DBFE BME BMT1 Supervisor Only MC68340 USER’S MANUAL Go to: www.freescale.com $020 1 0 SWIV0 1 1 $021 1 0 BMT0 0 0 MOTOROLA ...
Page 122
... Input Frequency 250 ms /EXTAL Input Frequency 1 s /EXTAL Input Frequency 8 s /EXTAL Input Frequency 32 s /EXTAL Input Frequency 128 s /EXTAL Input Frequency 512 s MC68340 USER’S MANUAL Go to: www.freescale.com 16.777-MHz External Clock Period 30 s 122 s 488 s 1.95 ms 15.6 ms 62.5 ms 250 ...
Page 123
... Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level 7 NOTE: MC68340 USER’S MANUAL Go to: www.freescale.com $022 PIV4 PIV3 PIV2 PIV1 PIV0 Supervisor Only ...
Page 124
... MOTOROLA For More Information On This Product SWP PTP PITR7 PITR6 PITR5 0 MODCK MODCK MC68340 USER’S MANUAL Go to: www.freescale.com $024 PITR4 PITR3 PITR2 PITR1 PITR0 Supervisor Only 4- 27 ...
Page 125
... For More Information On This Product Supervisor Only (2+2W+ CRYSTAL RSVD MC68340 USER’S MANUAL Go to: www.freescale.com $027 0 0 (Y+1) $004 SLIMP SLOCK RSTEN STSIM STEXT Supervisor Only MOTOROLA ...
Page 126
... The following paragraphs provide descriptions of the registers in the chip select function, and an example of how to program the registers. The chip select registers cannot be used until the V-bit in the MBAR is set. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 4- 29 ...
Page 127
... BA21 BA10 BA9 BA8 BFC3 BFC2 BFC1 MC68340 USER’S MANUAL Go to: www.freescale.com $044, $04C, $054, $05C BA20 BA19 BA18 BA17 BA16 Supervisor Only $046, $04E, $056, $05E ...
Page 128
... AM10 AM9 AM8 FCM3 FCM2 FCM1 where n = (number of bits set in MC68340 USER’S MANUAL Go to: www.freescale.com $040, $048, $050, $058 AM20 AM19 AM18 AM17 AM16 Supervisor Only $042, $04A, $052, $05A ...
Page 129
... Response 0 0 Zero Wait State 0 1 One Wait State 1 0 Two Wait States 1 1 Three Wait States Table 4-11. PSx Encoding PS0 Mode 0 0 Reserved 16-Bit Port 1 0 8-Bit Port External DSACK Response 1 1 MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 130
... NOTE PRTA5 PRTA4 PRTA3 PRTA2 PRTA1 (A30) (A29) (A28) (A27) (A26) (A25 Supervisor Only MC68340 USER’S MANUAL Go to: www.freescale.com $015 1 0 PRTA0 (A24 ...
Page 131
... NOTE DD6 DD5 DD4 DD3 DD2 DD1 Supervisor/User Supervisor/User MC68340 USER’S MANUAL Go to: www.freescale.com $017 $013 1 0 DD0 0 0 $011 MOTOROLA ...
Page 132
... DD6 DD5 DD4 DD3 DD2 DD1 Supervisor/User $019, 01B Supervisor/User MC68340 USER’S MANUAL Go to: www.freescale.com $01F 1 0 PPARB1 PPARB0 (IRQ1) (MODCK $01D 1 0 DD0 ...
Page 133
... Startup RESET is asserted by the MC68340 during the time in which V is locking onto the frequency, and the MC68340 is going through the reset operation. After RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the 32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot ROM ...
Page 134
... V-bit in the base address register before CS3 – CS1 can be used. Port A and B Registers • Program the desired function of the port A signals (PPARA1 and PPARA2 registers). • Program the desired function of the port B signals (PPARB register). MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 4- 37 ...
Page 135
... The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation includes chip select programming for external devices. * This code would be programmed beginning at offset $0 into ROM which is * relocated to address $60000 by the initialization code ...
Page 136
... MBAR is in CPU space load DFC to indicate CPU space Set address/valid bit write to MBAR X-bit doubles the default speed Set up a loop counter. Point to addr mask memory location. Init. addr mask and base addr reg MC68340 USER’S MANUAL Go to: www.freescale.com 4- 39 ...
Page 137
... CS1 - RAM - 00000000-0000ffff, fast termination CSAM1$ DC.L $0000FFF0 CSBAR1$ DC.L $00000005 * CS2 - external device - 00FFE8xx, external termination CSAM2$ DC.L $000000F3 CSBAR2$ DC.L $00FFE801 * CS3 - secondary memory - 00000000-0003ffff, 3-wait states, 16-bit term. CSAM3$ DC.L $0003FFFD CSBAR3$ DC.L $00000001 *************************************************************************** END 4-40 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 138
... HLL aids in the rapid development of complex algorithms with less error and is readily portable. The CPU32 instruction set will efficiently support HLL. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 1 ...
Page 139
... The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The 5-2 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 140
... Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination MOTOROLA For More Information On This Product, INSTRUCTION PREFETCH AND DECODE BUS CONTROL ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 MC68340 USER’S MANUAL Go to: www.freescale.com BUS CONTROL 5- 3 ...
Page 141
... The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. 5-4 For More Information On This Product, VECTOR BASE REGISTER (VBR) MC68340 USER’S MANUAL Go to: www.freescale.com 0 MOTOROLA ...
Page 142
... The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special- purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 5 ...
Page 143
... Swap Data Register Halves TAS Test and Set Operand TBLS, TBLSN Table Lookup and Interpolate, TBLU, TBLUN Table Lookup and Interpolate, TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink MC68340 USER’S MANUAL Go to: www.freescale.com Description Signed Unsigned MOTOROLA ...
Page 144
... The processor uses the privilege level indicated by the S-bit in the SR to select either the user or supervisor privilege level and either the user stack pointer (USP) or SSP for stack operations. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 7 ...
Page 145
... The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC, separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32-bit VBR (see Figures 5-3 and 5-4). 5-8 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 146
... CCR 15 0 A7' (SSP (CCR SFC DFC MC68340 USER’S MANUAL Go to: www.freescale.com DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER SUPERVISOR STACK POINTER STATUS REGISTER PROGRAM COUNTER ALTERNATE FUNCTION CODE REGISTERS 5- 9 ...
Page 147
... SUPERVISOR/USER STATE 5-10 For More Information On This Product, (CONDITION CODE REGISTER INTERRUPT PRIORITY MASK Figure 5-5. Status Register MC68340 USER’S MANUAL Go to: www.freescale.com USER BYTE EXTEND NEGATIVE ZERO OVERFLOW CARRY MOTOROLA ...
Page 148
... CPU32 can force the device into a low-power standby mode when immediate processing is not required. The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 11 ...
Page 149
... IMMEDIATE OPERAND OR SOURCE ADDRESS DESTINATION EFFECTIVE ADDRESS EXTENSION Figure 5-6. Instruction Word General Format 5-12 For More Information On This Product, OPERATION WORD SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) EXTENSION (IF ANY, ONE TO THREE WORDS) (IF ANY, ONE TO THREE WORDS) MC68340 USER’S MANUAL Go to: www.freescale.com 0 MOTOROLA ...
Page 150
... Examples: [7] is bit 7; [31:24] are bits 31–24 MOTOROLA For More Information On This Product, A register field of the instruction contains the number of the register. An effective address field of the instruction contains address mode information. The definition of an instruction implies the use of specific registers. MC68340 USER’S MANUAL Go to: www.freescale.com 5- 13 ...
Page 151
... Example: Source BCD source operand. LSW Least significant word MSW Most significant word {R/W} Read/write indicator In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow ( 5-14 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 152
... Shift and rotate System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 15 ...
Page 153
... BKPT # data BRA label Z; BSET Dn, ea BSET # data ea (SP BSR label Z; BTST Dn, ea BTST # data ea CHK ea ,Dn CHK2 ea ,Rn CLR ea cc CMP ea ,Dn CMPA ea ,An CMPI # data ea cc CMPM (Ay)+,(Ax)+ MC68340 USER’S MANUAL Go to: www.freescale.com Syntax MOTOROLA ...
Page 154
... PC JMP ea (SP) JSR ea PC LEA ea ,An (SP) LINK An,# displacement SP LPSTOP # data SR External Bus Interface (EBI) Destination LSd LSd LSd MOVE ea ea MOVEA ea ,An MOVE CCR, ea MC68340 USER’S MANUAL Go to: www.freescale.com Syntax 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q extend byte to word ...
Page 155
... NEGX ea NOP Destination NOT ea Destination OR ea ,Dn OR Dn, ea Destination ORI # data , ea CCR ORI # data ,CCR ORI # data ,SR SR (SP) PEA ea RESET ROd 1 Rx,Dy Destination ROd 1 # data ,Dy ROd 1 ea MC68340 USER’S MANUAL Go to: www.freescale.com Syntax ...
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... TBLSN. size Dym:Dyn, Dx TBLU. size ea ,Dx Dx TBLU. size Dym:Dyn, Dx TBLUN. size ea ,Dx TBLUN. size Dym:Dyn,Dx (SSP); TRAP # vector (SSP); SSP – 2 SSP; PC TRAPcc TRAPcc.W # data TRAPcc.L # data TRAPV Condition Codes TST ea An UNLK An MC68340 USER’S MANUAL Go to: www.freescale.com Syntax 5- 19 ...
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... – – MC68340 USER’S MANUAL Go to: www.freescale.com Special Definition (IR < LB > UB > UB) (R < LB ...
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... Dn [15:8]; ( Immediate Data Destination 32 SP – SP; (SP) An MC68340 USER’S MANUAL Go to: www.freescale.com Special Definition Source operand MSB Destination operand MSB Result operand MSB Register tested Bit Number Shift count Lower bound Upper bound NOT Rm Operation (SP) ...
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... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations. 5-22 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Dyn – Dym Temp (Temp Dn [7:0]) Temp (Dym 256) + Temp 8, 16, 32 Dyn – Dym Temp (Temp Dn [7:0]) / 256 Dym + Temp Dn MC68340 USER’S MANUAL Go to: www.freescale.com Destination Destination Destination Destination Destination Destination (signed or Destination Destination Destination (signed or Destination Destination Destination Destination Destination ...
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... Source Destination 8, 16, 32 Immediate Data 8, 16, 32 Destination Destination 8, 16, 32 Source V Destination 8, 16 16, 32 Immediate Data V Destination 8, 16, 32 Source – set condition codes MC68340 USER’S MANUAL Go to: www.freescale.com Operation Destination Destination Destination Destination Destination Destination Destination Destination MOTOROLA ...
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... Operand Size Operation bit number of destination destination bit number of destination destination bit number of destination destination bit number of destination MC68340 USER’S MANUAL Go to: www.freescale.com 0 X LSW Z bit bit bit ...
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... SP – 4 SP; PC (SP none Destination PC none SP – 4 SP; PC (SP); destination none Returns 16 (SP) PC none (SP) CCR none (SP) PC MC68340 USER’S MANUAL Go to: www.freescale.com Destination Destination Destination PC PC SP; (SP) PC MOTOROLA ...
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... TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA For More Information On This Product, LS — Low or same LT — Less than MI — Minus NE — Not equal PL — Plus T — True VC — Overflow clear VS — Overflow set MC68340 USER’S MANUAL Go to: www.freescale.com 5- 27 ...
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... If V set, then overflow TRAP exception Condition Code Register 8 Immediate Data CCR 8 Immediate Data CCR 16 Source CCR 16 CCR Destination 8 Immediate Data V CCR MC68340 USER’S MANUAL Go to: www.freescale.com SP; (SP) PC EBI; – (SSP); – (SSP); (vector) PC (SSP); (SSP); (SSP); PC (SSP) ...
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... Equal 0111 Overflow Clear 1000 Overflow Set 1001 Plus 1010 Minus 1011 Greater or Equal 1100 Less Than 1101 Greater Than 1110 Less or Equal 1111 MC68340 USER’S MANUAL Go to: www.freescale.com Test ...
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... All entries between these points fall on the line. Y 16384 5-30 For More Information On This Product, X Value Y Value 32768 1311 41472 1659 41728 1669 41984 1679 42240 1690 49152 1966 32768 49152 X INDEPENDENT VARIABLE Figure 5-7. Table Example 1 MC68340 USER’S MANUAL Go to: www.freescale.com X 49152. 65536 MOTOROLA ...
Page 168
... Table 5-14. MOTOROLA For More Information On This Product [8:15] = $A3 = 163 Dx [0:7] = $80 = 128 X = 65535 limited to 0 512 786 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 NOTE MC68340 USER’S MANUAL Go to: www.freescale.com 1023. 1024 5- 31 ...
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... Table 5-15, based on the function shown in Figure 5-9. 5-32 For More Information On This Product, X Value Y Value 512 1311 786 1966 LSR.W #6, [8:15 [0:7] = $8E = 142 (142 (1966 – 1311)) / 256 = 1674 MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... MC68340 USER’S MANUAL Go to: www.freescale.com 4096 ...
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... Dx [8:15 [0:7] = $D0 = 208 (208 (64 – 80)) / 256 = 67 0010 0000 . 0111 0000 0011 1111 . 0111 0000 0000 0001 . 0111 0000 MC68340 USER’S MANUAL Go to: www.freescale.com ...
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... Long addition avoids problems with carry Move radix point Fraction MSB in carry MC68340 USER’S MANUAL Go to: www.freescale.com 5- 35 ...
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... SR and an overview of actions taken by the processor in response to exception conditions. 5-36 For More Information On This Product, Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on FC2–FC0 refer to supervisor address spaces. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 37 ...
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... The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines. 5-38 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Level 5 Interrupt Autovector 078 SD Level 6 Interrupt Autovector 07C SD Level 7 Interrupt Autovector 080 SD Trap Instruction Vectors (0–15) 0BC — 0C0 SD (Reserved for Coprocessor) 0E8 — 0EC SD (Unassigned, Reserved) 0FC — 100 SD User-Defined Vectors (192) 3FC MC68340 USER’S MANUAL Go to: www.freescale.com Assignment 5- 39 ...
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... All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame. 5-40 For More Information On This Product, CAUTION MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. MOTOROLA For More Information On This Product, STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION ( WORDS) MC68340 USER’S MANUAL Go to: www.freescale.com ...
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... Suspends processing (instruction or exception); saves internal context. Exception processing is a part of instruction execution. Exception processing begins before instruction execution. Exception processing begins when current instruction or previous exception processing is complete. MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... All other internal peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 43 ...
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... PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION Figure 5-11. Reset Operation Flowchart 5-44 For More Information On This Product, ENTRY T0,T1 I2:I0 VBR . BUS ERROR BUS ERROR (VECTOR # 1) BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Address error exception processing begins when the processor attempts to use information from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 45 ...
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... BERR , the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK , the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations. 5-46 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 184
... They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector. MOTOROLA For More Information On This Product, 0000. MC68340 USER’S MANUAL Go to: www.freescale.com 5- 47 ...
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... Privilege violation vector offset, current PC, and SR are saved on the supervisor stack. The saved PC value is the address of the first word of the instruction causing the privilege violation. 5-48 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault. MOTOROLA For More Information On This Product, Table 5-18. Tracing Control T0 Tracing Function 0 No tracing 1 Trace on change of flow 0 Trace on instruction execution 1 Undefined; reserved MC68340 USER’S MANUAL Go to: www.freescale.com 5- 49 ...
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... Exception processing occurs as follows. First, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling 5-50 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... For a bus fault frame, the format value on the stack is first checked for validity. In addition, the version number on the stack must match the version number of the processor that is MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 51 ...
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... LG—Original operand size was long word SIZ—Remaining size of faulted bus cycle FUNC—Function code of faulted bus cycle 5-52 For More Information On This Product MC68340 USER’S MANUAL Go to: www.freescale.com $14 in the stack frame. The SIZ FUNC MOTOROLA ...
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... Instruction prefetch faults are distinguished from operand (both read and write) faults by the IN bit cleared, the error was on an operand cycle set, the error was on an instruction prefetch ignored during unstacking Operand 1 = Prefetch MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 53 ...
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... If a subsequent instruction attempts an operand access while a released write fault is pending, the instruction is aborted and the write fault is acknowledged. This action prevents stale data from being used by the instruction. 5-54 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... RW bit will show whether the fault was on a read or write. MOTOROLA For More Information On This Product MC68340 USER’S MANUAL Go to: www.freescale.com SIZ FUNC SIZ FUNC 5- 55 ...
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... PC of the instruction that caused the initial 5-56 For More Information On This Product MC68340 USER’S MANUAL Go to: www.freescale.com SIZ FUNC SIZ FUNC MOTOROLA ...
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... If the rerun bus cycle is a read, returned data will be ignored. MOTOROLA For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com 5- 57 ...
Page 195
... Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault. Consequently, MOVEM, like all other type II 5-58 For More Information On This Product, MC68340 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... MOTOROLA For More Information On This Product, $0E), and, if the frame being $02. MC68340 USER’S MANUAL Go to: www.freescale.com $10 ...
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... STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 0 VECTOR OFFSET STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW MC68340 USER’S MANUAL Go to: www.freescale.com 0 0 MOTOROLA ...
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... The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error. MOTOROLA For More Information On This Product $12). MC68340 USER’S MANUAL Go to: www.freescale.com SIZ FUNC 0 TRANSFER COUNT 5- 61 ...
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... RETURN PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW DBUF HIGH DBUF LOW CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD MC68340 USER’S MANUAL Go to: www.freescale.com 0 0 MOTOROLA ...
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... STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD MC68340 USER’S MANUAL Go to: www.freescale.com ...