IDT72510L35J Integrated Device Technology, Inc., IDT72510L35J Datasheet
IDT72510L35J
Specifications of IDT72510L35J
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IDT72510L35J Summary of contents
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... A Control Flags The IDT logo is a registered trademark of Integrated Device Techology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO trols will read or write Port B data blocks multiple times. The BiFIFOs have three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices. PIN CONFIGURATION INDEX D A10 D ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO PIN DESCRIPTIONS Symbol Name DA0-DA15 Data A DA16-DA17 Parity Chip Select Data Strobe Read/Write A A0, A1 Addresses DB0-DB7 Data B DB8 Parity B ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO PIN DESCRIPTIONS Symbol Name ACK Acknowledge CLK Clock FLGA-FLGD Flags RS Reset VCC Power GND Ground I/O O When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO DETAILED BLOCK DIAGRAM MUX Check Generate/ Parity Check Generate/ Parity MUX Register Byte Odd 5.31 COMMERCIAL TEMPERATURE RANGE 2669 drw 03 5 ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO FUNCTIONAL DESCRIPTION IDT’s BiFIFO family is versatile for both multiprocessor and peripheral applications. Data can be sent through both FIFO memories concurrently, thus freeing both processors from laborious direct memory access (DMA) protocols and ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO 36-BIT PROCESSOR to 18-BIT PERIPHERAL CONFIGURATION Processor Address Control Data RAM NOTE: 1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that Cntl A refers to W and . B talk ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO alone configuration BiFIFOs connected to a peripheral 36- to 9-bit configuration, the master device controls the bus. The Port B interface pins of the master device are outputs and the interface pins ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO 36-BIT PROCESSOR to 9-BIT PERIPHERAL CONFIGURATION Processor Address Control Data RAM NOTE Cntl A refers and IDT BiFIFO (Master) Cntl ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO PORT A RESOURCES Read FIFO 9-bit Bypass Path Configuration Registers Status Register 1 ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO RESET COMMAND FUNCTIONS Reset Function Operands 000 No Operation 001 Reset B A FIFO (Read, Write, and Rewrite Pointers = 0) 010 Reset A B FIFO (Read, Write, and Reread Pointers = 0) 011 ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO Status Register The Status Register reports the state of the programmable flags, the DMA read/write direction, the Odd Byte Register valid bit, and parity errors. The Status Register is read by CS setting = ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO CONFIGURATION REGISTER FORMATS 15 Config. Reg Config. Reg Config. Reg Config. Reg Config. Reg. ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO Port B Interface Port B also has parity, reread/rewrite and DMA functions. Port B can be configured to interface to either Intel-style ( Motorola-style ( , R/ ) devices ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO CONFIGURATION REGISTER 7 FORMAT BIT FUNCTION 0-7 Unused 8 Parity Input Control Parity Output Control Parity Odd/Even Control 11 Assign Parity Error to Flag A Pin 12-15 Unused ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO two parity error bits is brought out to FLG of Configuration Register 7. Parity generation creates the ninth bit. This ninth bit is placed on D for A->B read operation, and ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial V Terminal –0.5 to +7.0 TERM Voltage with Respect to Ground T Operating A Temperature T Temperature –55 to +125 BIAS Under Bias T Storage –55 to +125 ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO AC ELECTRICAL CHARACTERISTICS (Commercial 10 + Symbol Parameter RESET TIMING (Port A and Port B) t Reset cycle time RSC t Reset pulse ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO AC ELECTRICAL CHARACTERISTICS (Commercial 10 + Symbol Parameter PORT B PROCESSOR INTERFACE TIMING tb Port B access time with A1 no parity tb ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO AC ELECTRICAL CHARACTERISTICS (Commercial 10 + Symbol Parameter PORT B RETRANSMIT and PARITY TIMING RER REW LDRER, DSBH LDREW set-up ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO ( RER , REW LDRER LDREW REQ DS A FLG , A FLG C FLG B, FLG D t RSC t ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing Opcode D D ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO WRITE Input A17 READ Output A17 WPW ta WR ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO WRITE Input D – DS1 or NOTES: 1. tbDS1 and tbDH1 are with parity checking or if parity is ignored, ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO AÆB FIFO WRITE FLOW-THROUGH –D A0 A17 A B (1) Full Flag ( – NOTES: 1. Assume the flag pin is ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO BÆA FIFO WRITE FLOW-THROUGH –D A0 A17 (1) Full Flag – NOTES: 1. Assume the flag pin ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO BÆA READ BYPASS –D A0 A7, D A16 R DS ( BYD W ( BYD D –D ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO SINGLE WORD DMA TRANSFER t t CKH CLK REQ t REQS ACK WRITE Output B17 READ W ( ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO RER , REW LDRER, LDREW Figure 18. Port B Reread and Rewrite Timing for Intelligent Retransmit SET PARITY ERROR: FLGA IS ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO DS A Write ( Empty Flag B A Almost- Empty Flag Figure 20. Empty and Almost-Empty Flag Timing for BÆA ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO Write ( Empty Flag A B Almost-Empty Flag Figure 22. Empty and Almost-Empty Flag Timing for AÆB FIFO ...
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IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO ORDERING INFORMATION XXXXX L IDT Device Power Type XX J Speed Package Process/ Temperature Range 5.31 COMMERCIAL TEMPERATURE RANGE Blank Commercial ( + Plastic Leaded Chip Carrier 25 Commerical Only ...