MT90810AK Zarlink Semiconductor, MT90810AK Datasheet
MT90810AK
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MT90810AK Summary of contents
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... JTAG TDI TDO Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. Flexible MVIP Interface Circuit MT90810AK3 • Centralized voice processing systems • Voice/Data multiplexer Description Zarlink’s MT90810 is a Flexible MVIP Interface Circuit (FMIC) ...
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... LDI2 LDI3 90 EX8_KA 100 PIN PQFP EX8_KB 92 VSS FRAME 94 CLK8 FGA11 96 CLK4 CLK2 98 FGB11 FGA0 100 Figure 2 - Pin Connections Zarlink Semiconductor Inc Data Sheet 50 DREQ1 DREQ0 48 DACK1 DACK0 46 FGA7 ...
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... Frame Group B framing signals (Output). Programmable framing signals. The frame 9, 14, group outputs are determined by mode bits in the frame register to be either 28, 39, programmed outputs, output drive enables for DSi, or output framing pulses for use with 51, 62, local serial data streams. 76, 84, 99 MT90810 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... DMA reads/writes from/to the device. 10 TCK JTAG Input Clock (TTL Input). Maximum recommended clock rate is 16 MHz. If not used, this pin should be left unconnected. 11 TDI JTAG Serial Input Data (TTL Input). If not used, this pin should be left unconnected. MT90810 Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... RAM. Samples are written into this data RAM in a fixed order and read out in an order determined by the programming of the connection memory. An input shift register and holding latch for each input stream make up the serial to parallel conversion blocks on the input of MT90810 Description 5 Zarlink Semiconductor Inc. Data Sheet ...
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... If the DSi or DSo channel is programmed as an input, the corresponding DSo or DSi channel will automatically be configured as an output. Thus, there are always 256 MVIP input and 256 MVIP output channels or 256 full duplex MVIP channels on the MVIP bus. Figure 3 - “Per channel direction control” illustrates the use of DC MT90810 6 Zarlink Semiconductor Inc. Data Sheet ...
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... MVIP frame (8 kHz). This state machine can either free run or synchronize kHz source such as the MVIP F0 signal or an external 8 kHz reference. Refer to Figure 4 - “Clock Control Functional Block Diagram” for further details. MT90810 DC=0 for stream 0 channel 1 I/P FMIC DC=1 for stream 0 channel 29 Figure 3 - Per-channel Direction Control 7 Zarlink Semiconductor Inc. Data Sheet DSo0 I/P O ...
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... EX_8KB Digital PLL 3, 7 16MHz (sampler) FRAME Jittery 4.096MHz 4 60ns peak jitter PLL_MODE 4.096MHz 2 div 4 External 8kHz 8kHz FMIC state machine 8 Zarlink Semiconductor Inc. Data Sheet 0 SEL_S8K 1 SEC8K 2 EN_SEC8K Analog PLL PLL_LO up/ Phase Comparator down external loop filter 16MHz div VCO ...
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... Jitter transfer function of the digital PLL and analog PLL combination is determined primarily by the digital PLL. The digital PLL is essentially a digital sampler which samples on the nearest rising or falling edge of its 16 MHz clock and therefore has jitter on the output. MT90810 10 100 1K Frequency, log scale (Hz) 9 Zarlink Semiconductor Inc. Data Sheet 10K 100K ...
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... In mode 1, the first four outputs of the frame group FGx[0:3] are available for programmed output as in mode 0. The other 8 outputs of each frame group are available as output drive enables for the MVIP DSI/DSO channels within the streams. FGA4 to FGA11 outputs correspond to output drive enables for the MVIP DSo channels within streams MT90810 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Throughput Delay min Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t. Mb/s t.s. Table 1 - Throughput Delay Values 11 Zarlink Semiconductor Inc. Data Sheet max ...
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... LAR and AMR register to select high or low connection memory and then either reading from or writing to the IDR. MT90810 Register MCS - Master Control/Status Register LAR - Low Address Register AMR - Address Mode Register IDR - Indirect Data Register Table 2 - FMIC I/O Addresses 12 Zarlink Semiconductor Inc. Data Sheet ...
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... The data for write requests is actually staggered by one DMA request for each stream. This means that the data written into the device due to a DMA write request of a given channel, is not actually written to that channel but to the next channel enabled for DMA on the same stream. MT90810 13 Zarlink Semiconductor Inc. Data Sheet ...
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... Two bits in the register SEL_XIN or VCO_BYP may be set if the user wishes to bypass the internal analog PLL or VCO, respectively. The bits are defined in Table 17 - “Diagnostic (DIAG_REG) Register”. MT90810 Description (This register is cleared upon reset) Bit Function Table 4 - Low Address Register [01] 14 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 6 - Indirect Data Register [1] Clock Control Register Local Output Clock Control Local Serial Configuration Register RESERVED Frame Group A start register Frame Group A mode register Frame Group B start register Frame Group B mode register RESERVED Chip diagnostic bits 15 Zarlink Semiconductor Inc. Data Sheet Function ...
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... MVIP_MST bit in MCS is set. FMIC as MVIP Slave • FMIC is entirely slaved to MVIP bus timing. • MVIP C4 is selected as input to APLL. • State machine is synchronized to MVIP C4 and F0 inputs. • MVIP_MST bit in MCS register must be cleared. 16 Zarlink Semiconductor Inc. Data Sheet Function ...
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... When set, inverts 8.192 MHz CLK8 output pin When set, inverts 4.096 MHz CLK4 output pin When set, inverts 2.048 MHz CLK2 output pin When set, inverts FRAME output signal RESERVED SER_CNFG Zarlink Semiconductor Inc. Data Sheet Function ...
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... LDI/O[0] = local stream 0 LDI/O[1] = local stream 1 channel 0 channel 1 channel 2 channel 3 etc.... 18 Zarlink Semiconductor Inc. Data Sheet LDI/O[0] = local stream 0 LDI/O[1] = local stream 1 LDI/O[2] = local stream 2 LDI/O[3] = local stream 3 LDI/O[0] LDI/O[2] (4 MHz MHz, 64 channels) channels) stream0, ch0 ...
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... FRM_TYPE MODE [10/11 PROG_OUT(7: RESERVED STRT(7: FRMx_STRT) Register Description Table 13 - Frame Group Mode Bits 19 Zarlink Semiconductor Inc. Data Sheet PROG_OUT(11: PROG_OUT(3: BIT_RATE STRT ...
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... Programmed Output All 4 bits are driven out FGx[11:8] Table 14 - Frame Register Bits for Mode 0 Frame Group Mode 1 [01] DSi/DSo output enable All 4 bits are driven out FGx[3:0] Table 15 - Frame Register Bits for mode 1 20 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Upper three bits of the 11 bit quantity specified in Table 13 - “Frame Group Mode bits” Description Channels decimal 0:31 0:31 0:31 32:63 0:31 64:95 0:31 96:127 0:31 128:159 0:31 160:191 0:31 192:223 0:31 224:255 0:31 256:287 0:31 288:319 Table 18 - Data Memory Mapping 21 Zarlink Semiconductor Inc. Data Sheet Indirect RAM Address hex 0x00:0x1f 0x20:0x3f 0x40:0x5f 0x60:0x7f 0x80:0x9f 0xa0:0xbf 0xc0:0xdf 0xe0:0xff 0x100:0x11f 0x120:0x13f ...
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... MVIP Stream 0 MVIP Stream 1 MVIP Stream 2 MVIP Stream 3 MVIP Stream 4 MVIP Stream 5 MVIP Stream 6 MVIP Stream 7 Local Stream 0 Local Stream 1 Local Stream 2 Local Stream 3 CAB7 Description 22 Zarlink Semiconductor Inc. Data Sheet Indirect RAM Address hex 0x140:0x15f 0x160:0x17f Channels 0:31 0:31 0:31 0:31 0:31 0:31 0:31 0:31 0:31 0:31 0:31 0:31 ...
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... LD0:0 LD1:0 Table 22 - Connection Memory High Bits for Local Channels MT90810 OE/CE RESERVED DC/CSTo Figure 11 - Connection Memory High Byte Description Description LD2:0 LD3:0 LD0:1 LD1:1 LD2:1 LD3:1 23 Zarlink Semiconductor Inc. Data Sheet CAB8 0 LD0:2 LD1:2 LD2:2 LD3:2 LD0:3 ...
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... BOUNDARY -SCAN CELL(BSC) T BSC BSC TEST DATA IN (TDI) BSC BSC TEST CLOCK (TCK CORE LOGIC T TEST MODE R O SELECT (TMS BSC BSC BSC BSC TEST DATA OUT (TDO) R Figure Typical Boundary-Scan IC 24 Zarlink Semiconductor Inc. Data Sheet ...
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... This instruction is used to BYPASS the FMIC while performing boundary- scan testing on other devices with scan registers in the same serial register chain. The FMIC is allowed to function normally. This instruction is automatically loaded upon reset of the FMIC, as specified in IEEE1149.1 Table 23 - Instruction Register 25 Zarlink Semiconductor Inc. Data Sheet ...
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... DSi[7:0] F0, C4, C2, SEC8K tristate enable for FRAME, CLK8, CLK4, CLK2, CSTo tristate enable for ALL output only pins EX8KA, EX8KB LDO[3:0] LDI[3:0] D[7:0] tristate enable for D[7:0] RDY, ERR, DREQ[1:0] RD, WR, CS, ALE, A[1:0], DACK[1:0] Table 24 - Boundary Scan Register 26 Zarlink Semiconductor Inc. Data Sheet ...
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... - Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - ° 125 °C Units Test Conditions V °C Units Test Conditions ...
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... C4P t 110 122 134 C4H t 110 122 134 C4L t 474 488 502 C2P t 220 244 268 C2H t 220 244 268 C2L 28 Zarlink Semiconductor Inc. Data Sheet Test Conditions ns Load Cap =200pF ns For all Timing ...
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... DSI Output DSO Input DSI Input Note: *MVIP Output streams are high impedance during the first cycle of Bit 7 MT90810 t C4P t t C4L C4H t C2P t C2H t FH BIT Figure 13 - MVIP Stream Timing 29 Zarlink Semiconductor Inc. Data Sheet t C2L t PD BIT 6-0 ...
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... LDO LDI (8 MHz Bit Rate LDO t S LDI Note: *Timing for CLK is shown for LOC_CLK register set to xxxx0010 MT90810 t C8H t C4P t C4H t C2P t C2L Figure 14 - Local Stream Timing 30 Zarlink Semiconductor Inc. Data Sheet t C2H ...
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... MHz Clock (FMIC Internal Signal) t FGA [0:11] FGB [0:11] MT90810 PD Figure 15 - Local Frame Timing 31 Zarlink Semiconductor Inc. Data Sheet ...
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... FGx1 FGx2 Notes either A for frame group for frame group B. 12 framing pulses per group, FGx0 to FGx11 are available in PQFP package. Figure 16 - Frame Pulse Timing for Mode 2 MT90810 bit cells 32 Zarlink Semiconductor Inc. Data Sheet ...
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... FRH LDS t 10 LDH FRAME FSC CLK4 DCL FMIC LDO DU/DD LDI DU/DD Figure 17 - FMIC to GCI Connections 33 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 256 ns Load Cap = 200pF for all timing 134 ns 150 ns 150 GCI device ...
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... Sym. Min. Typ. Max AH DAC t ACC 50 800 t 25 RDY DOFF 34 Zarlink Semiconductor Inc. Data Sheet Ch. 0 Ch. 0 Bit 3 Bit 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V Units Test Conditions ns Load Cap = 100pF for all timing ...
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... RDY is only driven low during memory (slow) cycles measured from either going high, whichever is later. DOFF Figure 20 - Intel Multiplexed Bus Timing for Read Cycle (ALE is active) MT90810 t t ACC ACC 35 Zarlink Semiconductor Inc. Data Sheet t AH DAC t DOFF t DH Read Data t DOFF t DAC ...
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... Figure 21 - Intel Multiplexed Bus Timing for Write Cycle (ALE is active) A[0:1] R/W [WR [RD] CS DTACK AD[0:7] Figure 22 - Motorola Non-multiplexed Bus Timing for Read Cycle (ALE=VDD) MT90810 t AH Write Data t DAC t ACC t RDY t ACC t DAC 36 Zarlink Semiconductor Inc. Data Sheet DOFF Read Data ...
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... WR pulse width (DMA=fast write) MT90810 t ACC Sym. Min. Typ. Max. Units t CDAK1 DMA t CDAK0 controller t dependent DAKR t DAKW CDRQ1 CDRQ0 RDRQ WDRQ t 100 RW t 100 WW 37 Zarlink Semiconductor Inc. Data Sheet Test Conditions ...
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... DREQ1 DACK1 RD DREQ0 DACK0 WR Note: DMA Read and Write cycles are asynchronous to C2o. C2o t CDRQ DREQ/1 async DACK0/1 WR/RD MT90810 t CDAK0 t DAKR t DAKW Figure 24 - DMA Interface Timing t WDRQ t RDRQ Figure 25 - DMA Timing Detail A 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...