GAL26V12C-20LPI Lattice Semiconductor Corp., GAL26V12C-20LPI Datasheet

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GAL26V12C-20LPI

Manufacturer Part Number
GAL26V12C-20LPI
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Lattice Semiconductor Corp.
Datasheet
• HIGH PERFORMANCE E
• LOW POWER CMOS
• E
• TWELVE OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26V12, at 7.5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
ance available of any 26V12 device on the market. E
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL
erase/rewrite cycles.
Copyright ©2000 Lattice Semiconductor Corp. GAL, E
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
FEATURES
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
DESCRIPTION
2
CELL TECHNOLOGY
2
) floating gate technology to provide the highest perform-
®
Advanced CMOS Technology
®
products. LATTICE also guarantees 100
2
CMOS
®
2
TECHNOLOGY
CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
2
technol-
INPUT/CLK 2
VCC
FUNCTIONAL BLOCK DIAGRAM
PACKAGE DIAGRAMS
I/CLK 1
I
I
I
I
I
I
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
11
5
7
9
12
4
GAL26V12
Top View
PLCC
14
2
High Performance E
16
28
18
26
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Generic Array Logic
GAL26V12
RESET
PRESET
10
12
14
16
16
14
12
10
8
8
8
8
I/CLK1
I/CLK2
OLMC 10
OLMC 11
OLMC 4
OLMC 5
OLMC 0
OLMC 3
OLMC 6
OLMC 7
OLMC 8
OLMC 9
OLMC 1
OLMC 2
Vcc
I
I
I
I
I
I
I
I
I
I
I
November 2000
1
7
14
2
26V12
CMOS PLD
GAL
DIP
28
21
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
INPUT
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TM

Related parts for GAL26V12C-20LPI

GAL26V12C-20LPI Summary of contents

Page 1

... Copyright ©2000 Lattice Semiconductor Corp. GAL CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc- tor Corp. The specifications herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. ...

Page 2

... Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. PART NUMBER DESCRIPTION GAL26V12C Device Name Speed (ns Low Power Power Specifications GAL26V12 ...

Page 3

OUTPUT LOGIC MACROCELL (OLMC) The GAL26V12 has a variable number of product terms per OLMC. Of the ten available OLMCs, four OLMCs have access to eight product terms (pins 15, 16, 26 and 27), two have ten prod- uct terms ...

Page 4

REGISTERED MODE CLK1 ACTIVE LOW REGISTERED OUTPUT WITH BURIED FEEDBACK Selects CLK1 Selects CLK2 ...

Page 5

COMBINATORIAL MODE ACTIVE LOW COMBINATORIAL OUTPUT WITH I/O FEEDBACK Selects CLK1 Selects CLK2 CLK1/ CLK2 S P ACTIVE LOW COMBINATORIAL OUTPUT WITH ...

Page 6

GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP 0000 0052 . . . 0468 2 0520 . . . 0936 3 0988 . . . . 1508 4 1560 . . . . . 2184 5 ...

Page 7

GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP (CONT 3900 . . . . . . . 4732 9 4784 . . . . . . 5512 10 5564 . . . . . 6136 11 6188 . ...

Page 8

... One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Icc specified for a ten-bit binary counter pattern. 4) Typical values are at Vcc = 5V and T A Specifications GAL26V12C Specifications GAL26V12 (1) RECOMMENDED OPERATING COND. Commercial Devices: ...

Page 9

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. CAPACITANCE ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Guaranteed but not 100% tested. Specifications GAL26V12C Specifications GAL26V12 Over Recommended Operating Conditions -7 MIN. MAX. MIN. MAX. — 7.5 — — 4.5 — — 2 — ...

Page 10

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. CAPACITANCE ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Guaranteed but not 100% tested. Specifications GAL26V12C Specifications GAL26V12 Over Recommended Operating Conditions MIN. MAX. — — — 7 6.5 0 71.4 105.2 125 — ...

Page 11

SWITCHING WAVEFORMS INPUT or VALID INPUT I/O FEEDBACK t COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O to Output Enable/Disable CLK Clock Width INPUT or I/O FEEDBACK DRIVING AR t ...

Page 12

DESCRIPTIONS max with External Feedback 1/( Note: fmax with external feedback is cal- culated ...

Page 13

ELECTRONIC SIGNATURE An electronic signature is provided in every GAL26V12 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available ...

Page 14

POWER-UP RESET Circuitry within the GAL26V12 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low after a specified time (tpr, 1μs MAX result, the state on ...

Page 15

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - ...

Page 16

TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.3 1.2 1.1 1 0.9 0.8 0.7 4.50 4.75 5.00 5.25 5.50 ...

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