M306H5FGFP Renesas Electronics Corporation., M306H5FGFP Datasheet
M306H5FGFP
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M306H5FGFP Summary of contents
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... DATA ACQUISITION CONTROLLER 1. DESCRIPTION The M306H5MG/MC-XXXFP and M306H5FGFP are single-chip microcomputers using the high-perfor- mance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 116-pin plastic molded QFP. This single-chip microcomputer operates using sophisticated instructions featuring a high level of instruction efficiency ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table of contents 1. DESCRIPTION ...................................................... 1 1.1 Features ........................................................... 1 1.2 Applications ..................................................... 1 1.3 Pin Configuration ............................................. 3 1.4 Performance Outline ........................................ 4 1.5 Block Diagram ................................................. 6 2. OPERATION OF FUNCTIONAL BLOCKS ............ 10 2.1 Memory ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 1.3 Pin Configuration Figures 1.3.1 shows the pin configuration (top view ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 1.4 Performance Outline Table 1.4 performance outline. Table 1.4.1 Performance outline Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port Input ...
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... M306H5MG-XXXFP/MC-XXXFP/FGFP Figure 1.4.2 Product table Type No. M306H5MG-XXXFP M306H5MC-XXXFP M306H5FGFP Type No – Figure 1.4.1 Type No, Memory Size, and Package Rev.1.20 Dec 13, 2005 page 5 of 323 REJ03B0095-0100Z RAM capacity Package type ROM capacity 256K bytes 8K bytes 5K bytes 116P6A-A 128K bytes ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 1.5 Block Diagram Figure 1.5 block diagram Port P0 Port P1 Port P2 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Watchdog timer (15 bits) DMAC (2 channels) Figure 1.5.1 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 1.5.1 Pin Description Pin name Signal name Power supply CC1 CC2 input V SS CNV CNV Input SS SS RESET Reset input Input X Clock input Input IN X Clock output Output OUT BYTE ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 1.5.2 Pin Description Pin name Signal name I/O port P5 Input/output 0 7 Output WRL / WR, WRH / BHE, Output Output RD, Output BCLK, Output HLDA, Input HOLD, ALE, Output RDY Input P6 to ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 1.5.3 Pin Description Pin name Signal name Power supply input Power supply input SVREF Synchronous Input slice level input CVIN1 Composite Input video signal input 1 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2. OPERATION OF FUNCTIONAL BLOCKS 2.1 Memory Figure 2.1 memory map of M306H5/MG-XXXFP/MC-XXXFP/FCFP. The address space extends the 1M bytes from address 00000 The internal ROM is allocated in a lower address direction beginning with address FFFFF ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.2 Central Processing Unit (CPU) Figure 2.2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 R2 R3 b15 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Frame Base Register (FB configured with 16 bits, and is used for FB relative addressing. (4) Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. (5) ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.3 Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 2.3.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Notes 1: When the START pin=H, apply the clock of 20 cycles or more to the X When the START pin=L, apply the clock of 20 cycles or more to the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP CIN td(P-R) More than 20 cycles are needed (Note) Microprocessor mode BYTE = H RESET BCLK Address RD WR CS0 Microprocessor mode BYTE = L Address RD WR CS0 Single chip mode Address ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.3.1. Pin Status When RESET Pin Level is “L” Pin name CNV P0 Input port P1 Input port P2, P3 Input port Input port Input port 5 7 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.3.4 SFR Address 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 0004 16 Processor mode register 1 0005 16 System clock control register 0 0006 16 System clock control register 1 0007 16 Chip select ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address 0040 16 0041 16 0042 16 0043 16 INT3 interrupt control register 0044 16 Timer B5/SLICE ON interrupt control register 0045 16 0046 Timer B4/Remote control interrupt control register, UART1 BUS collision detection interrupt 16 control register 0047 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 01B0 16 01B1 16 01B2 16 01B3 16 01B4 16 Flash memory control register 1 01B5 16 01B6 16 Flash memory control ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address 0340 Timer B3 count start flag 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034A 16 034B 16 034C 16 034D 16 034E 16 034F ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address 0380 Count start flag 16 Clock prescaler reset flag 0381 16 0382 One-shot start flag 16 Trigger select register 0383 16 0384 Up-down flag 16 0385 16 0386 Timer A0 register 16 0387 16 0388 Timer A1 register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address 03C0 A-D register 0 16 03C1 16 03C2 A-D register 1 16 03C3 16 03C4 A-D register 2 16 03C5 16 03C6 A-D register 3 16 03C7 16 03C8 A-D register 4 16 03C9 16 03CA A-D register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.4 Processor Mode (1) Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 2.4.1 shows the features of these processor modes. Table 2.4.1. Features of Processor Modes ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Processor mode register 0 (Note Bit symbol Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). Note 2: Effective when ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Processor mode register 1 (Note Bit symbol (b6-b4) Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Single-chip mode 00000 16 SFR 00400 16 Internal RAM XXXXX 16 Can not use YYYYY 16 Internal ROM FFFFF 16 Note 1: Set the PM10 bit to “0” (08000 Note 2: In case of PM13 bit is “0”, available ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.4.1 Bus During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/output to and from external devices. These bus control pins include A _______ _____ ________ ______ ________ ________ to CS3, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.4.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. (1) Address Bus The address bus consists of 20 lines bits by using the PM06 bit in the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two cycles. Access to ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Memory expansion mode 00000 16 SFR 00400 16 Internal RAM XXXXX 16 Reserved area 04000 16 08000 16 Reserved, External area 10000 16 27000 Reserved area 16 28000 16 30000 16 External area D0000 16 Reserved area YYYYY 16 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (4) Read and Write Signals When the data bus is 16 bits wide, the read and write signals can be chosen combination of RD, ________ ______ BHE and combination of RD, WRL and ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP ________ (6) The RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on ________ the RDY pin is asserted low at the last falling edge of BCLK of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (7) Hold Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the __________ input on HOLD pin is pulled low, the microcomputer is placed in a hold ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.4.8. Pin Functions for Each Processor Mode Processor mode 00 PM05–PM04 bits Data bus width BYTE pin I/O ports ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (9) External Bus Status When Internal Area Accessed Table 2.4.9 shows the external bus status when the internal area is accessed. Table 2.4.9. External Bus Status When Internal Area Accessed Item ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.4.10. Bit and Bus Cycle Related to Software Wait PM1 register Area Bus mode PM17 bit SFR 0 Internal RAM, ROM 1 0 Separate bus External area 1 Multiplexed bus (Note 2) 1 Note 1: To use the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Separate bus, No wait setting Write signal Read signal Data bus Address bus (2) Separate bus, 1-wait setting Write signal Read signal Data bus Address bus (3) Separate bus, 2-wait setting Write signal Read signal Data bus Address ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Separate bus, 3-wait setting BCLK Write signal Read signal Data bus Address bus (2)Multiplexed bus 2-wait setting BCLK Write signal Read signal Address bus Address bus/ Data bus (3)Multiplexed bus, 3-wait setting BCLK Write signal Read ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.5 Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit Table 2.5.1 lists the clock generation circuit specifications. Figure 2.5.1 shows the clock generation cir- ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP START CM07 CM06 CM10=1(stop mode) WAIT instruction RESET Software reset NMI Interrupt request level judgment output CM02, CM04, CM05, CM06, CM07: CM0 register bits CM10, CM11, CM16, CM17: CM1 register bits PCLK0, PCLK1: PCLK register bits Figure 2.5.1. Clock ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP System clock control register 0 (Note Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Note 1: Write to this register after setting the PRC0 bit of PRCR register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP System clock control register 1 (Note Bit symbol CM10 (b4-b1) CM15 CM16 CM17 Note 1: Write to this register after setting the PRC0 bit of PRCR ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Peripheral clock select register (Note Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable). Processor mode register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.5.1 Oscillator Circuit The following describes the clocks generated by the clock generation circuit. Two oscillation circuits are built in the clock generating circuit, and a main clock or a sub clock can be chosen as a CPU clock ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Set the main clock division ratio. Set the CM17 to the CM16 bits to “002,” set the CM06 bit to Note 1: Change After the oscillation of the main clock becomes stable enough. Note 2: Setting No division of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.5.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. (1) CPU Clock and BCLK These are operating clocks for the CPU and watchdog ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.5.3 Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. (1) Normal Operation Mode Normal operation mode is further classified into ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. Because the main clock and sub clock, are on, the peripheral functions using ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.5.2. Pin Status During Wait Mode Pin _______ _______ CS0 to CS3 ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ HLDA,BCLK ALE I/O ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.5.4. Pin Status in Stop Mode Pin _______ _______ CS0 to CS3 ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ HLDA, BCLK ALE ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Figure 2.5.8 shows the state transition from normal operation mode to stop mode and wait mode. Figure 2.5.9 shows the state transition in normal operation mode. All oscillators stopped CM10=1 Stop mode Interrupt Interrupt CM07=0 CM06=1 CM05=0 Stop mode ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Main clock oscillation High-speed mode CPU clock: f CM07=0 CM06=0 CM17=0 CM16=0 High-speed mode CPU clock: f CM07=0 CM06=0 CM17=0 CM16=0 Sub clock oscillation Notes: 1: Switch clock after oscillation of main clock is sufficiently ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.5.4 System Clock Protective Function When the main clock is selected for the CPU clock source, this function disables the clock against modi- fications in order to prevent the CPU clock from becoming halted by run-away. If the PM21 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.6 Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 2.6.1 shows the PRCR register. The following lists the registers pro- tected ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7 Interrupts 2.7.1 Type of Interrupts Figure 2.7.1 shows types of interrupts. Software (Non-maskable interrupt) Interrupt Hardware Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions. Note 2: Do not normally use this interrupt because it ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow Interrupt An overflow interrupt occurs when executing ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. _______ • NMI Interrupt _______ An NMI interrupt is generated when input on the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 2.7.2 lists the relocatable vector tables. Setting an even address in the INTB register results ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Interrupt control register (Note Note 1: This bit can only be reset by writing "0" (Do not write "1"). Note 2: To rewrite the interrupt control registers ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. IR Bit The IR ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.6 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here interrupt occurs during execution of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Interrupt Response Time Figure 2.7.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP The operation of saving registers carried out in the interrupt sequence is dependent on whether the (Note the time of acceptance of an interrupt request, is even or odd. If the stack pointer even, the FLG ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the REIT instruction at the end of the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 Timer B4/Remote control, UART1 bus collision INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3/HINT, UART0 bus collision Timer B5/SLICEON UART1 reception, ACK1 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP ______ 2.7.7 INT Interrupt _______ INTi interrupt (i triggered by the edges of external inputs. The edge polarity is selected using the IFSR register's IFSRi bit. _______ _______ INT4 and INT5 share the interrupt vector and ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP ______ 2.7.8 NMI Interrupt _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI interrupt input pin ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.7.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Address match interrupt enable register Address match interrupt enable register Address match interrupt register (b19) (b16) ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.8 Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP CPU clock HOLD Write to WDTS register RESET Figure 2.8.1. Watchdog Timer Block Diagram Watchdog timer control register Note 1: The WDC5 bit is always “1” (warm start) no matter how ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.9 DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU interven- tion. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.9.1. DMAC Specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred DMA request factors (Note 1, Note 2) Channel priority Transfer unit Transfer address direction Transfer mode •Single transfer Transfer is completed when the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP DMA0 request cause select register Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below. DSEL3 to ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP DMA1 request cause select register Bit symbol Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP DMAi source pointer ( (Note) (b19) (b16)(b15) (b23 Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of DMiCON ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.9.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) When the transfer unit bits and the source of transfer is an even address BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) When the transfer unit is 16 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.9.2 Number of DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the number of DMA transfer cycles. Table 2.9.3 shows the Coefficient j, k. The number of DMAC ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.9.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register ( “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.9.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.10 Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP f 1 • Main clock 1 C32 TB0 IN TB1 IN TB2 IN TB3 IN TB4 IN TB5 IN Note: Be aware that TB5 Figure 2.10.2. Timer ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.10.1 Timer A Figure 2.10.3 shows a block diagram of the timer A. Figures 2.10.4 to 2.10.6 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Ai register ( (Note 1) (b15) (b8 Note 1: The register must be accessed in 16 bit units. Note 2: If the TAi register is set to ‘0000 requests are not generated ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP One-shot start flag Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode). Note 2: Overflow or underflow Trigger select register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Timer Mode In timer mode, the timer counts a count source generated internally (see Table 2.10.1). Figure 2.10.7 shows TAiMR register in timer mode. Table 2.10.1. Specifications in Timer Mode Item Count source f Count operation • Down-count ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 2.10.2 lists specifica- tions in ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Ai mode register (i (When not using two-phase pulse signal processing Bit symbol TMOD0 TMOD1 Note 1: During event counter mode, the count source can ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.10.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Count source Count operation Divide ratio 1/ (FFFF for down-count Count start condition Count stop condition ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Ai mode register (i (When using two-phase pulse signal processing Note 1: TCK1 bit is valid for timer A3 mode register. No matter ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 2.10.4.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 2.10.10 shows the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Ai mode register (i Bit symbol Note 1: TA0 pin is N-channel open drain output. OUT Note 2: Effective when the TAiTGH and TAiTGL bits ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (4) Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 2.10.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 2.10.11 shows ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Ai mode register ( Note 1: TA0 pin is N-channel open drain output. OUT Note 2: Effective when the TAiTGH and TAiTGL bits of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Count source “H” Input signal to TA pin iIN “L” “H” PWM pulse output from TA pin iOUT “L” IR bit of TAiIC “1” register “0” Frequency of count source ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.10.2 Timer B Figure 2.10.14 shows a block diagram of the timer B. Figures 2.10.15 and 2.10.16 show registers related to the timer B. Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Timer Bi register (i=0 to 5)(Note 1) (b15) (b8 Pulse width modulation mode Note 1: The register must be accessed in 16 bit units. Note 2: The timer counts pulses from an external device or overflows ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Timer Mode In timer mode, the timer counts a count source generated internally (see Table 2.10.6). Figure 2.10.17 shows TBiMR register in timer mode. Table 2.10.6. Specifications in Timer Mode Item Count source f Count operation • Down-count ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 2.10.7) . Figure 2.10.20 shows TBiMR register in event counter mode. Table 2.10.7. Specifications ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 2.10.8). Figure 2.10.21 shows TBiMR register in pulse period ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches “0000 ” 16 “1” TBiS bit “0” “1” TBiIC register's IR bit “0” “1” TBiMR register's MR3 bit “0” The TB0S to TB2S ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11 Serial I/O Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. 2.11.1 UARTi (i UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (UART0) RxD polarity RxD 0 reversing circuit Clock source selection CLK1 to CLK0 1SIO or 2SIO Internal 01 2 CKDIR=0 f 8SIO 32SIO External CKDIR=1 CKPOL Clock synchronous type (when internal clock ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP No reverse RxD data RxDi reverse circuit Reverse 1SP PAR disabled STPS PAR 2SP STPS= 1 PAR enabled 0 0 PAR 2SP enabled STPS PAR STPS = 0 1SP PAR disabled i=0 to ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UARTi transmit buffer register (i=0 to 2)(Note) (b15) (b8 Note: Use MOV instruction to write to this register. UARTi receive buffer register (i (b15) (b8 Note 1: When the UiMR register’s ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UARTi transmit/receive mode register (i Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Note 1: Set the corresponding port direction bit for each CLKi pin to “0” ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UARTi transmit/receive control register 1 (i= Bit symbol (b5-b4) UiLCH UiERE UART2 transmit/receive control register Bit symbol ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UART transmit/receive control register Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP (b7) Note: When using multiple transfer clock output pins, make sure the following conditions are met: U1MR ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UARTi special mode register 2 (i Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI (b7) UARTi special mode register 3 (i ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP UARTi special mode register 4 (i Bit symbol STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 Note: Set to “0” when each condition is generated. Figure 2.11.8. U0SMR4 to ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.2 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 2.11.1 lists the specifications of the clock synchronous serial I/O mode. Table 2.11.2 lists the registers used ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2. 11. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit UiTB(Note3 UiRB(Note3 OER UiBRG UiMR(Note3) SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 2.11.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 2.11.4 lists the P6 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Example of transmit timing (when internal clock is selected) Transfer clock “1” UiC1 register “0” Write data to the UiTB register TE bit “1” UiC1 register TI bit “0” “H” CTSi “L” CLKi TxDi D 0 “1” UiC0 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (a) CLK Polarity Select Function Use the UiC0 register ( 2)’s CKPOL bit to select the transfer clock polarity. Figure 2.11.10 shows the polarity of the transfer clock. (1) When the UiC0 register’s CKPOL bit = ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (c) Continuous Receive Mode When the UiRRM bit ( (continuous receive mode), the UiC1 register’s TI bit is set to “0” (data present in the UiTB register) by reading the UiRB register. In ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP _______ _______ (f) CTS/RTS Separate Function (UART0) This function separates CTS from the P6 pin. To use this function, set the register bits as shown below. 4 • U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) • U0C0 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.3 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 2.11.5 lists the specifications of the UART mode. Table 2.11.5. UART Mode Specifications ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2. 11. 6. Registers to Be Used and Settings in UART Mode Register Bit UiTB UiRB OER,FER,PER,SUM Error flag UiBRG UiMR SMD2 to SMD0 CKDIR STPS PRY, PRYE IOPOL ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.7 lists the functions of the input/output pins during UART mode. Table 2.11.8 lists the P6 functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock UiC1 register “1” TE bit “0” UiC1 register TI bit “1” “0” “H” CTSi “L” Start bit TxDi ST UiC0 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source “1” UiC1 register RE bit “0” RxDi Transfer clock Reception triggered when transfer clock “1” is generated by falling ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (b) Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 2.11.18 shows serial data ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP _______ _______ (d) CTS/RTS Separate Function (UART0) This function separates CTS from the P6 pin. To use this function, set the register bits as shown below. 4 • U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) • U0C0 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.4 Special Mode mode is provided for use as a simplified I 2 fications of the I C mode. Table 2.11.10 to 2.11.11 lists the registers used in the I register values set, Table ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP SDAi STSPSEL=1 Delay circuit STSPSEL=0 ACK=1 ACK=0 ACKD register Noise Filter Start condition detection Stop condition detection Falling edge detection SCLi IICM=0 I/O port STSPSEL=0 UARTi IICM=1 Noise Filter This diagram applies to the case where the UiMR register's ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table2.11.10. Registers to Be Used and Settings in I Register Bit UiTB Set transmission data (Note 3) UiRB Reception data can be read (Note 3) 8 ACK or NACK is set in this ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.11. Registers to Be Used and Settings in I Register Bit UiSMR4 STAREQ Set this bit to “1” to generate start condition RSTAREQ Set this bit to “1” to generate restart condition STPREQ Set this bit to “1” ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2 Table 2.11.12 Mode Functions Clock synchronous serial I/O Function mode (SMD2 to SMD0 = 001 IICM = 0) Factor of interrupt number 6, 7 and 10 (Note Factor of interrupt number UARTi transmission ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) 1st bit 2nd bit 3rd bit SCLi SDAi (2) IICM2= 0, CKPH= 1 (clock delay) 1st bit 2nd bit 3rd bit SCLi D7 D ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • Detection of Start and Stop Condtion Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.13. STSPSEL Bit Functions Function Output of SCLi and SDAi pins Star/stop condition interrupt request generation timing (1) When slave CKDIR=1 (external clock) STSPSEL bit 0 SCLi SDAi Start condition detection interrupt (2) When master CKDIR=0 (internal clock), ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 2.11.24. The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register “1” (ACK data output), the value ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.5 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 2.11.14 lists the specifications of Special Mode 2. Table 2.11.15 lists the registers used in Special Mode 2 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP CLK 2( P7 RxD 1( P7 TxD 0( Microcomputer (Master) Figure 2.11.25. Serial Bus Communication Control Example (UART2) Rev.1.20 Dec 13, 2005 page 142 of 323 REJ03B0095-0100Z ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.15. Registers to Be Used and Settings in Special Mode 2 Register Bit UiTB(Note3 UiRB(Note3 OER UiBRG UiMR(Note3) SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP • Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register’s CKPH bit and the UiC0 register’s CKPOL bit. Make sure the transfer clock polarity and phase are ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" (Note) Data input timing Note :UART2 output is an N-channel open drain and must be pulled-up externally. ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.6 Special Mode 3 (IE mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 2.11.16 lists the registers used in IE mode and the register values set. Figure 2.11.29 shows ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) UiSMR register ABSCS bit (bus collision detect sampling clock select) Transfer clock TxDi RxDi Timer Aj Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2 (2) UiSMR register ACSE bit (auto clear of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.7 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TxD2 pin when a ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.18. Registers to Be Used and Settings in SIM Mode Register Bit U2TB(Note U2RB(Note OER,FER,PER,SUM Error flag U2BRG U2MR SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL U2C0 CLK1, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Transmission Transfer clock “1” U2C1 register TE bit “0” “1” U2C1 register TI bit “0” Start bit TxD Parity error signal sent back from receiver RxD pin level (Note) “1” U2C0 register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Figure 2.11.31 shows the example of connecting the SIM interface. Connect T pull-up. Figure 2.11.31. SIM Interface Connection (a) Parity Error Signal Output The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”. • ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (b) Format • Direct Format Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH bit to “0”. • Inverse Format Set the PRY bit to “0”, UFORM bit to “1” ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.11.8 SI/O3 and SI/O4 SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 2.11.34 shows the block diagram of SI/O3 and SI/O4, and Figure 2.11.35 shows the SI/O3 and SI/O4- related registers. Table 2.11.19 shows the specifications of SI/O3 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP S I/Oi control register ( (Note symbol Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Table 2.11.19. SI/O3 and SI/O4 Specifications Item Transfer data format Transfer clock Transmission/reception start condition Interrupt request generation timing CLKi pin fucntion S i pin function OUT SINi pin function Select function Note 1: To set the SiC register’s ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (a) SI/Oi Operation Timing Figure 2.11.36 shows the SI/Oi operation timing 1.5 cycle (max) "H" SI/Oi internal clock "L" "H" CLKi output "L" Signal written to the "H" "L" SiTRR register S i output "H" OUT "L" "H" S ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (c) Functions for Setting the SiC register’s SMi6 bit = 0 (external clock), the S transferring. Figure 2.11.38 shows the timing chart for setting an S (Example) When “H” selected for S Signal written to SiTRR ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.12 A-D Converter The microcomputer contains one A-D converter circuit based on 8-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10 ___________ and P9 . Similarly TRG the corresponding ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP f 1/3 AD Software trigger AD TRG V REF VCUT VCUT=1 Successive conversion register OPA0=1 ANEX 0 OPA1=1 ANEX 1 Figure 2.12.1. A-D Converter Block Diagram Rev.1.20 Dec 13, 2005 page 159 of 323 REJ03B0095-0100Z A-D conversion ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 2 (Note Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: The Ø frequency ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) One-shot Mode In this mode, the input voltage on one selected pin is A-D converted once. Table 2.12.2 shows the specifications of one-shot mode. Figure 2.12.4 shows the ADCON0 to ADCON1 registers in one-shot mode. Table 2.12.2. One-shot ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: After rewriting ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Repeat mode In this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 2.12.3 shows the specifications of repeat mode. Figure 2.12.5 shows the ADCON0 to ADCON1 registers in repeat mode. Table 2.12.3. Repeat ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. Note 2: After rewriting ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Single Sweep Mode In this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 2.12.4 shows the specifications of single sweep mode. Figure 2.12.6 shows the ADCON0 to ADCON1 registers in ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (4) Repeat Sweep Mode 0 In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 2.12.5 shows the specifications of repeat sweep mode 0. Figure 2.12.7 shows the ADCON0 to ADCON1 registers in repeat sweep ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (5) Repeat Sweep Mode 1 In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the se- lected pins. Table 2.12.6 shows the specifications of repeat sweep mode 1. Figure 2.12.8 shows ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP A-D control register 0 (Note Bit symbol Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate. A-D control register 1 (Note 1) ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (a) Sample and Hold If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 cycles for 8-bit resolution. Sample-and-hold is effective in all operation modes. ØAD Select whether ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (d) Current Consumption Reducing Function When not using the A-D converter, its resistor ladder and reference voltage input pin (V separated using the ADCON1 register’s VCUT bit. When separated, no current will flow from the V into the resistor ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (f) Caution of Using A-D Converter (1) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.13 CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X The CRC code consists of 16 bits which are generated for each data block in ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Setup procedure and CRC operation when generating CRC code “80C4 (a) CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.14 Expansion Function 2.14.1 Expansion function description Expansion function cousists of CRC operation function, data slice function and humming decoder function. Each function is controled by expansion memories. (1) CRC operation function It performs error detection of a code, ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.14.2 Expansion memory Expansion function memory is divided by 3 patterns ; Slice RAM, CRC registers and expansion regis- ters (Humming decoder operates by the register placed on SFR). Data writing and read out to the Slice RAM, CRC ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.14.3 RAM Slice Slice RAM stores 18-line slice data. There are several types of Slice data : PDC, VPS, VBI, XDS, WSS, etc. All data are stored to addresses which corresponds to slice line (ex. 22 line' data is ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP The each head address of the address is corresponded to slice line following slice information. SR00F to SR004 0 Line register 3 Line register 2 0 Line register Other Note : * the first field : ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.14.4 CRC Operation Circuit (EPG-J) CRC operation circuit (EPG- circuit for performing error detection and error correction by the 272-190 shortening difference set cyclic code which is a coding system in a data multiplex broadcast. CRC register ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP For accessing to CRC register data, set accessing address (CA3 to CA0) (shown in Table 2.14.3) to CRC register address control register (address 0212 register data control register (address 0214 control register increments address automatically. Then, next address data ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (1) Reset of CRC remainder bit CRC remainder bit is automatically reset by CRCON=0 (address control register for CRC registers). (2) Setting 00 16 The data set as the DAOUT register is shifted from the low rank side of ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP ; ; Equations (Constant definition) ; _CRC_ADRS .equ _CRC_DATA .equ SLICE_WORD_NUM .equ ; ; Macro definition ; _wait .macro nop nop nop .endm ; ; CRC operation routine ; ;------ Writing of code data ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- mov.w #0000H mov.w #9010H ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Bit composition of a CRC register (1) Address 00 (=CA3 CD15 CD8CD7 Rev.1.20 Dec 13, 2005 page 186 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name The code data shift register DAOUT0 write-in bit 0 The ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Address 01 (=CA3 CD8CD7 CD15 Rev.1.20 Dec 13, 2005 page 187 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name The CRC bit error CRC_ERR00 detection bit The CRC bit ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Address 02 (=CA3 CD15 CD8CD7 Rev.1.20 Dec 13, 2005 page 188 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name 81th remainder polynomial CRC_81 coefficient bit 80th remainder polynomial CRC_80 coefficient bit 79th remainder polynomial CRC_79 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (4) Address 03 (=CA3 CD8CD7 CD15 Rev.1.20 Dec 13, 2005 page 189 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name 65th remainder polynomial CRC_65 coefficient bit 64th remainder polynomial CRC_64 coefficient bit 63th remainder polynomial CRC_63 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (5) Address 04 (=CA3 CD8CD7 CD15 Rev.1.20 Dec 13, 2005 page 190 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name 49th remainder polynomial CRC_49 coefficient bit 48th remainder polynomial CRC_48 coefficient bit 47th remainder polynomial CRC_47 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (6) Address 05 (=CA3 CD8CD7 CD15 Rev.1.20 Dec 13, 2005 page 191 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name 33th remainder polynomial CRC_33 coefficient bit 32th remainder polynomial CRC_32 coefficient bit 31th remainder polynomial CRC_31 ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (7) Address 06 (=CA3 CD15 CD8CD7 (8) Address 07 (=CA3 CD15 CD8CD7 Rev.1.20 Dec 13, 2005 page 192 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name 17th remainder polynomial CRC_17 coefficient bit 16th ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (9) Address 08 (=CA3 CD15 CD8CD7 (10) Address 09 (=CA3 CD8CD7 CD15 (11) Address 0A (=CA3 CD15 CD8CD7 (12) Address 0B (=CA3 CD15 CD8CD7 (13) Address 0C ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (14) Address 0D (=CA3 CD15 CD8CD7 Rev.1.20 Dec 13, 2005 page 194 of 323 REJ03B0095-0100Z CD0 Bit symbol Bit name Reserved bit Nothing is assigned. The value is unfixed when it reads. Function ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP 2.14.5 Expansion Register Control Data slice function. Expansion register composition is shown in Table 2.14.4. Table 2.14.4 Expansion register composition Rev.1.20 Dec 13, 2005 page 195 of 323 REJ03B0095-0100Z ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP For accessing to expansion register data, set accessing address (DA5 to DA0) (shown in Table 2.14.4) to expansion register address control register (address 0216 DD0) to expansion register data control register (address 0218 expansion register address control register increments ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP Bit composition of an expansion register (1) Address 00 (=DA5 DD15 DD8DD7 Rev.1.20 Dec 13, 2005 page 197 of 323 REJ03B0095-0100Z DD0 Bit symbol Bit name The 0th line state register LN0_EV0 selection bit The 1st ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (2) Address 01 (=DA5 DD8DD7 DD15 Rev.1.20 Dec 13, 2005 page 198 of 323 REJ03B0095-0100Z DD0 Bit symbol Bit name The 0th line state register LN0_EV1 selection bit The 1st line state register LN1_EV1 selection bit ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (3) Address 02 (=DA5 DD15 DD8DD7 (4) Address 03 (=DA5 DD15 DD8DD7 Rev.1.20 Dec 13, 2005 page 199 of 323 REJ03B0095-0100Z DD0 Bit symbol Bit name Nothing is assigned. The 16th line state ...
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M306H5MG-XXXFP/MC-XXXFP/FGFP (5) Address 04 (=DA5 DD15 DD8DD7 Rev.1.20 Dec 13, 2005 page 200 of 323 REJ03B0095-0100Z DD0 Bit symbol Bit name The 0th line state register LN0_OD0 selection bit The 1st line state register LN1_OD0 selection bit ...