TMPR4927ATB-200 TOSHIBA Semiconductor CORPORATION, TMPR4927ATB-200 Datasheet

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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA RISC PROCESSOR TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... IU D$(32K I$(32K) GPR MMU BIU MAC WB FPU TX49/H2 CPU Core IM bus ACLC UART Timer Figure 1 TX4927 Internal Block Diagram TOSHIBA RISC PROCESSOR TMPR4927ATB-200 G I 64bit Gbus bus bridge IRC PIO SDRAMC DMAC External BUS Controller External BUS Interface ...

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... SDRAMC DMAC External BUS Controller External BUS Interface PCIC IM bus bridge IRC PCI Bus 32 PCI Devices User logic PCIC TMPR4927ATB-200 SDRAM Control SDRAM Memory signals Devices External System Bus ( Data : 64bit, Address : 20bit ) Control Signals ROM/ Ext. Flash/ I/O SRAM Dev. EJC-TMPR4927ATB-3 ...

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... Built-in Debug Support Unit (DSU) TOSHIBA RISC PROCESSOR TX49/H2 Core CP0 CP0 Registers MMU/TLB Pipeline Exception Unit Control CP1 FPU 32KB 32KB Write 4-way set 4-way set Buffer Instruction Data Cache Cache Figure 3 TX49/H2 Core Block Diagram TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... Supports memory-to-memory copy mode, with no address boundary restrictions Supports burst transfer double words for a single read / write Supports memory fill mode, writing double-word data to specified memory area Supports chained DMA transfer TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... The TX4927 contains a 2-channels asynchronous serial I/O interface ( full duplex UART ). 2-channel full duplex UART Built-in baud rate generator FIFOs 8-bit x 8 transmitter FIFO 13-bit ( 8 data bits and 5 status bits ) x 16 receiver FIFO Supports DMA tranfer TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... Supports playback for 16-bit surround, center, and LFE channels Supports audio recording and layback at variable rate Supports Line1 and GPIO slots for modem CODEC Supports AC-link low power mode, wakeup, and warm reset Supports input / output of sample data by DMA transfer TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... IEEE1149.1 and real-time debugging using a debug support unit ( DSU ) built into the TX49/H2 core. IEEE 1149.1 JTAG Boundary Scan Real-time debugging functions using special emulation probe : execution control ( execution, break, step, and register / memory access ) and PC trace TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB Jan / 02 TOSHIBA CORPORATION ...

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... B11 TCK D1 PIO[7] B12 DCLK D2 Vss B13 TDO D3 PIO[6] B14 PCST[8] D4 VddIN B15 PCST[5] D5 BYPASSPLL* B16 PCST[2] D6 Vss TOSHIBA RISC PROCESSOR TMPR4927ATB-200 D7 CE[0]* E23 PCIAD[22] D8 VddIN E24 PCIAD[21] D9 Vss E25 PCIAD[20] D10 VddIN E26 PCIAD[19] D11 DMAACK[0] F1 INT[2] D12 VddIO F2 INT[1] D13 ...

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... VddIO AA26 DATA[56] U25 DATA[61] AB1 DATA[45] U26 Vss AB2 DATA[13] V1 Vss AB3 DATA[44] V2 Vss AB4 DATA[12] TOSHIBA RISC PROCESSOR TMPR4927ATB-200 AB5 Vss AC21 Vss AB6 DQM[0] AC22 DATA[48] AB7 VddIO AC23 VddIN AB8 Vss AC24 Vss AB9 ADDR[3] AC25 DATA[53] ...

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... TOSHIBA RISC PROCESSOR TMPR4927ATB-200 E26 F26 G26 H26 J26 E25 F25 G25 H25 J25 E24 F24 G24 H24 J24 E23 F23 G23 H23 J23 E22 F22 ...

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... TOSHIBA RISC PROCESSOR TMPR4927ATB-200 W26 Y26 AA26 AB26 AC26 W25 Y25 AA25 AB25 AC25 W24 Y24 AA24 AB24 AC24 W23 Y23 AA23 AB23 AC23 W22 Y22 AA22 AB22 AC22 ...

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... SDRAM. H: Separate devices other than SDRAM from the data bus. L: Connect devices other than SDRAM to the data bus. Separation and connection are performed using external bi-directional bus buffers (such as the 74xx245). TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... Synchronous Memory Device Chip Select Chip select signals for SDRAM. O RAS* Row Address Strobe RAS signal for SDRAM. O CAS* Column Address Strobe CAS signal for SDRAM. O WE* Write Enable WR signal for SDRAM. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... ECC/parity check bit signals. The bits correspond to the following data bus signals:. CB[7] : DATA[63:54], CB[6] : DATA[53:48] CB[5] : DATA[47:40], CB[4] : DATA[39:32] CB[3] : DATA[31:24], CB[2] : DATA[23:16] CB[1] : DATA[15:8], CB[0] : DATA[7:0] CB[7:0] share pins with the PIO[15:8] signals for parallel I/O. The boot configuration signal on the ADDR[18] pin selects between PIO[15:8] and CB[7:0]. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... The function of these signals can be selected from BE[3:0]* and BWE[3:0]* by using the DATA[5] signal and the EBCCRn and BC registers in the External Bus Controller during boot-mode configuration. I/O ACK* / Acknowledge READY PU Flow control signal. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function BE[1]* / BWE[1]* : DATA[15:8] BE[0]* / BWE[0]* : DATA[7:0] EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... PCICLK Enable field of the pin configuration register (PCFG.PCICLKEN[5:0]). I PCICLKIN PCI feedback clock input PCI feedback clock input. I/O PCIAD[31:0] PCI Address and Data Multiplexed address and data bus. I/O C_BE[3:0] Bus Command and Byte Enable Command and byte enable signals. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... PCI bus arbiter is used. In internal arbiter mode, REQ[3:2]* are PCI bus request input signals. In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed in the input state, they must be pulled up externally. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... Indicates an address parity error, a data parity error in a special cycle fatal error. In host mode, SERR input signal. In satellite mode, SERR open-drain output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... This is a clock signal for a serial EEPROM for PCI configuration. Timer Interface O TIMER[1:0] Timer Pulse Width Output Timer output signal. I TCLK External Timer Clock PU Timer input clock. TMR0, TMR1 and TMR2 share this signal. OD WDRST* Watchdog Reset Watchdog reset output signal. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... PIO[15:8] and CB[7:0]. I/O PIO[7:0] PIO Ports Parallel I/O signals. PIO[4:2] share pins with the AC-link interface signals (SDOUT, SDIN[0], and BITCLK). The boot configuration signal on the ADDR[9] pin selects between PIO[4:2] and AC-link interface signals. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... BITCLK shares the pin with the PIO[2] signal. The boot configuration signal on the ADDR[9] pin selects between BITCLK and PIO[2]. Interrupt Signals I NMI* Non Mask-able Interrupt PU Non-Mask-able interrupt input. I INT[5:0] External Interrupt Requests PU The external interrupt request signals. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... A clock output for a real-time debug system. The timing of a serial monitor bus and PC trace interface signal are all defined by this debug clock DCLK. 3 divide the operation clock of the TMPR4927TB at the time of a serial monitor bus operation. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... PLL Reset This pin must be fixed to High. I CGRESET* CG Reset CGRESET* initializes the CG Reset signals I RESET* Reset Reset signal. Test signals I TEST[4:0]* Test mode Enable PU Test pins. These pins must be left open or fixed to High. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... Power and Ground pins to internal PLL circuit. PLL2Vdd_A, PLL1Vcc_A and PLL2Vcc_A = 1.5V, PLL1Vss_A, PLL1_Vss_A and PLL2_Vss_A = GND PLL2Vss_A - VddIN Internal Power Pins Power pins at 1.5V - VddIO I/O Power Pins Power pins at 3.3V - Vss Ground Digital ground pins. Vss = 0 V. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Function EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... CB[7:0] / PIO[15:8] DMAREQ[2] / ACRESET* DMAACK[2] / SYNC PIO[4:2] / SDOUT, SDIN[0], BITCLK Table 4.2 Setting by ADDR[18] PIO[15:8] I/O Table 4.3 Setting by ADDR[9] ADDR[9]=1 (ACLC) ADDR[9]=0 (Non ACLC) O ACRESET SYNC O O SDOUT I/O I SDIN[0] I/O I BITCLK I/O TMPR4927ATB-200 ADDR[18]=1 (ECC) CB[7:0] DMAREQ[2] DMAACK[2] PIO[4] PIO[3] PIO[2] EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... Operating Case Temperature (*3) Functional operation should be restricted to the recommended operating conditions. Those are the limits under which proper device operation is guaranteed. Therefore, the end product must be designed within the recommended voltage and temperature ranges indicated. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 (*1) SYMBOL RATING 0.3 to 3.9 VddIO ...

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... I (* IL2 (* IH1 IN CCIO I (* IH2 IN CCIO I (*10 VddIO = 3.3V, CCInt VddIN = 1.6V, MASTERCLK=100MHz PClock = 200MHz I VddIO = 3.5V, CCIO VddIN = 1.5V, MASTERCLK=100MHz PClock = 200MHz Load=25pF TMPR4927ATB-200 0.1V, Vss = 0V) MIN. MAX. UNIT -0.3 0.8 V 2.0 VddIO+0 - ...

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... OLPCI OUT I 0 < V < VddIO IHPCI IN I ILPCI I (*3) OZPCI TX4927 VddIN VddIN PLL1Vdd_A PLL2Vdd_A PLL1Vss_A PLL2Vss_A Vss Vss SYMBOL AS a reference Value R L T.B. 1.5V TMPR4927ATB-200 0.1V, Vss = 0V) MIN. MAX. UNIT -0.5 0.9 V 1.8 VddIO+0.3 V VddIO 0 VddIO 0 ...

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... Power On AC Characteristics PARAMETER PLL stable time CGRESET* width time RESET* width time VddIN, VddIO, PLL1Vdd_A, MASTERCLK stable time PLL2Vdd_A MASTERCLK CGRESET * RESET * TOSHIBA RISC PROCESSOR TMPR4927ATB-200 ( VddIO = 3.3V 0.2V, VddIN = 1.5V SYM CONDITION t ADDR[2]=H in boot time MCP f ADDR[2]=H in boot time MCK t MCH ...

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... DATA[63:0] I/O 50 16mA - - (*1) An SDRAM bus transaction can complete in no more than two clock cycles through programming the SDRAMC and Configuration registers. TOSHIBA RISC PROCESSOR TMPR4927ATB-200 ( VddIO = 3.3V 0.2V, VddIN = 1.5V SYM Descriptions Tcyc_sdclk Clock Cycle Time Thigh_sdclk Clock High Time Tlow_sdclk ...

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... INTEGRATED CIRCUIT SDCLK OUTPUT INPUT Output Signals and when bypass mode input Signals (SDCLK basis) SDCLK SDCLKIN INPUT When non bypass mode input signals (SDCLK basis) TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Tval_* Tsu_* Th_* inputs valid Tbp Th_* Tsu_* inputs valid outputs valid ...

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... Output Delay for ACK* (High <-> Low) Tval_ackv Output Delay for ACK* (Hi-Z -> valid) Tval_ackz Output Delay for ACK* ( valid -> Hi-Z) - Tsu_ack ACK* Setup Time Th_ack ACK* Hold Time Tcyc_sysclk Thigh_sysclk Tval_* outputs valid Th_* External Bus Interface TMPR4927ATB-200 0.2V, VddIN = 1.5V 0.1V 0V) SS MIN MAX (ns) (ns 1.5 6.5 1.5 8.5 1 ...

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... Output Delay (point to point connection) - Tpps66 Setup Time (point to point connection) - Tpph66 Hold Time (point to point connection) Tppd33 Output Delay (point to point connection) - Tpps33 Setup Time (point to point connection) - Tpph33 Hold Time (point to point connection) TMPR4927ATB-200 MIN MAX (ns) (ns 1 ...

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... Thigh66/Thigh33 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc PCICLKIN (Vcc=3.3V) Tsu66/Tsu33/Tpps66/Tpps33 Th66/Th33/Tpph66/Tpph33 INPUT inputs valid PCICLK[n] PCICLK [except for n] n TOSHIBA RISC PROCESSOR TMPR4927ATB-200 Tcyc66/Tcyc33 Tlow66/Tlow33 Tval66/Tval33/Tppd66/Tppd33 OUTPUT PCI Interface (3.3V) Tcyco66/Tcyco33 Thigho66/Thigho33 Tlowo66/Tlowo33 Tskw PCI Clock Skew Tslew66/Tslew33 0.4 Vcc p-to-p (minimum) outputs valid EJC-TMPR4927ATB-35 ...

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... INTEGRATED CIRCUIT 6. Package TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...

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... Added the Package Diagram 22/Jan/01 DC/AC Timing 26/Jan/01 Modify the description 6/Feb/01 Modify the description 20/Aug/01 Modify the Signal description and AC Characteristics 17/Jan/02 Modify the product name TMPR4927TB -> TMPR4927ATB-200 Modify the spec of AC and DC TOSHIBA RISC PROCESSOR TMPR4927ATB-200 EJC-TMPR4927ATB- Jan / 02 TOSHIBA CORPORATION ...