M5M54R08AJ-12 Renesas Electronics Corporation., M5M54R08AJ-12 Datasheet
M5M54R08AJ-12
Related parts for M5M54R08AJ-12
M5M54R08AJ-12 Summary of contents
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REJ09B0340-0200 16 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual This user's manual is written for the M30245 group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual explains a function of the ...
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The figure of each register configuration describes its functions and attributes as follows : ...
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Table of Contents Chapter 1. Hardware ............................................................ 1 Chapter 2. Peripheral Functions Usage ............................. 3 2.1 Protect ............................................................................................................................. 4 2.1.1 Overview .................................................................................................................................................. 4 2.1.2 Protect Operation .................................................................................................................................... 5 2.2 Timer A ............................................................................................................................ 6 2.2.1 Overview .................................................................................................................................................. 6 2.2.2 Operation of ...
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Operation of Serial Interface Special Function (reception in master mode with clock delay) ........................................................................................................................................... 98 2.5.4 Operation of Serial Interface Special Function (transmission in slave mode ............................... 102 without delay) ...................................................................................................................................... 102 2.5.5 Operation of Serial Interface Special Function ...
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Overview ............................................................................................................................................ 253 2.12.2 Operation of Watchdog Timer (Watchdog timer interrupt) ........................................................... 256 2.13 Address Match Interrupt Usage .............................................................................. 258 2.13.1 Overview of the address match interrupt usage ............................................................................ 258 2.13.2 Operation of Address Match Interrupt ............................................................................................ 260 2.14 ...
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Memory to 8-bit Width Data Bus Connection Example .......................................................... 337 4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example .............................. 338 4.3.5 Chip Selects and Address Bus .......................................................................................................... 339 4.4 Connectable Memories .............................................................................................. 340 ...
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Chapter 1 Hardware ...
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See M30245 group datasheet. ...
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Chapter 2 Peripheral Functions Usage ...
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M30245 Group 2.1 Protect 2.1.1 Overview 'Protect function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by ...
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M30245 Group 2.1.2 Protect Operation The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 and frequency Operation synthesizer-related registers causes system clock ...
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M30245 Group 2.2 Timer A 2.2.1 Overview The following is an overview for timer A, a 16-bit timer. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is ...
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M30245 Group (3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency ...
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M30245 Group Figure 2.2.1. Memory map of timer A-related registers Timer Ai mode register ( Figure 2.2.2. Timer A-related registers (1) Rev.2.00 Oct 16, 2006 page 8 of ...
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M30245 Group Timer Ai register ( (Note 1) (b15 b8 Mode Timer mode Event counter mode One-shot timer mode 16-bit PWM 8-bit PWM Note 1 : Read and write data in 16-bit ...
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M30245 Group Up/down flag (Note Trigger select register Figure 2.2.4. Timer A-related registers (3) Rev.2.00 Oct 16, 2006 page 10 of 354 REJ09B0340-0200 Symbol ...
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M30245 Group Clock prescaler reset flag One-shot start flag Figure 2.2.5. Timer A-related registers (4) Rev.2.00 Oct 16, 2006 page 11 of 354 ...
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M30245 Group 2.2.2 Operation of Timer A (timer mode) In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up ...
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M30245 Group Selecting timer mode and functions Setting divide ratio (b15) (b8) b7 Setting clock prescaler reset flag (This function is effective when f dividing the X by 32.) CIN b7 b0 Setting count ...
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M30245 Group 2.2.3 Operation of Timer A (timer mode, gate function selected) In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 ...
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M30245 Group Selecting timer mode and functions Note: Set the corresponding port direction register to “0”. Setting divide ratio (b15) b7 Setting clock prescaler reset flag (This function is effective when f dividing ...
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M30245 Group 2.2.4 Operation of Timer A (timer mode, pulse output function selected) In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are described below. Figure 2.2.10 shows the operation timing, and Figures ...
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M30245 Group Selecting timer mode and functions Note: The setting of the corresponding port register and the direction register are invalid. Setting divide ratio (b15) (b8 Setting clock prescaler reset flag ...
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M30245 Group 2.2.5 Operation of Timer A (event counter mode, reload type selected) In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items are described below. Figure 2.2.12 shows the operation timing, and ...
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M30245 Group Selecting event counter mode and functions b7 b0 Timer Ai mode register (i [Address 0396 TAiMR (i Selection of event counter mode Pulse output function select bit ...
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M30245 Group 2.2.6 Operation of Timer A (event counter mode, free run type selected) In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items are described below. Figure 2.2.14 shows the operation timing, ...
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M30245 Group Selecting event counter mode and functions Selection of event counter mode Pulse output function select bit Count polarity select bit Up/down switching cause select bit 0 (Must always be ...
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M30245 Group 2.2.7 Operation of timer A (two-phase pulse signal process in event counter mode, normal mode selected) In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.6. Operations of the circled items ...
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M30245 Group Selecting event counter mode and functions Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”. Two-phase pulse ...
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M30245 Group 2.2.8 Operation of timer A (two-phase pulse signal process in event counter mode, multiply-by-4 mode selected) In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.7. Operations of the circled items ...
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M30245 Group Selecting event counter mode and functions Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”. Two-phase pulse signal ...
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M30245 Group 2.2.9 Operation of Timer A (one-shot timer mode) In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items are described below. Figure 2.2.20 shows the operation timing, and Figures 2.2.21 shows ...
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M30245 Group Selecting one-shot timer mode and functions Clearing timer Ai interrupt request bit Setting one-shot timer's time (b15 (b8 Setting clock prescaler reset flag (This function ...
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M30245 Group 2.2.10 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.10. Operations of the circled items are described below. Figure 2.2.22 shows the ...
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M30245 Group Selecting PWM mode and functions b7 b0 Timer Ai mode register (i [Address 0396 TAiMR (i Selection of PWM mode 1 (Must always be “1” in PWM mode) ...
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M30245 Group Setting clock prescaler reset flag (This function is effective when f by dividing the X by 32.) CIN b7 b0 Clock prescaler reset flag [Address 0381 CPSRF Clock prescaler reset flag effect 1 : Prescaler ...
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M30245 Group 2.2.11 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the circled items are described below. Figure 2.2.25 shows the ...
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M30245 Group Selecting PWM mode and functions b7 b0 Timer Ai mode register (i [Address 0396 TAiMR (i Selection of PWM mode 1 (Must always be “1” in PWM mode) ...
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M30245 Group Setting clock prescaler reset flag (This function is effective when f by dividing the X by 32.) CIN b7 b0 Clock prescaler reset flag [Address 0381 CPSRF Clock prescaler reset flag effect 1 : Prescaler ...
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M30245 Group 2.2.12 Precautions for Timer A (timer mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai ...
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M30245 Group 2.2.13 Precautions for Timer A (event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer ...
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M30245 Group (5) In the case of using as “Free-Run type”, the timer register contents may be unknown when counting begins. If the timer register is set before counting has started, then the starting value will be unknown. • In ...
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M30245 Group 2.2.14 Precautions for Timer A (one-shot timer mode) (1) At reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Setting the count start ...
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M30245 Group 2.2.15 Precautions for Timer A (pulse width modulation mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) The timer ...
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M30245 Group 2.3 Clock-Synchronous Serial I/O 2.3.1 Overview Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. (1) Transmission/reception format 8-bit data (2) Transfer rate If ...
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M30245 Group The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from: _______ _______ • CTS/RTS functions disabled _______ • CTS function only enabled _______ • RTS function only enabled (b) Function for choosing CLK polarity This ...
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M30245 Group cessive reception mode disabled (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, slect the function select register A to I/O port and set the direction register to ...
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M30245 Group UARTi transmit buffer register ( (Note) b15 b8 (b7) (b0 Bit Symbol UARTi receive buffer register ( b15 b8 (b7) (b0 Bit Symbol Note 1: Always write “0”. ...
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M30245 Group UARTi bit rate generator (o (Note ...
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M30245 Group ...
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M30245 Group 2.3.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are described below. Figure 2.3.5 shows ...
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M30245 Group Example of wiring Example of operation (1) Transmission enabled (2) Confirming CTS (3) Start transmission Tc Transfer clock “1” Transmit enable bit (TE) “0” Data is set to UARTi transmit buffer register “1” Transmit buffer empty “0” flag ...
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M30245 Group Setting UARTi transmit/receive mode register (i Setting UARTi transmit/receive control register 0 (i Note 1: Set the corresponding port direction register to “0”. ...
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M30245 Group Setting UARTi bit rate generator ( Can be set to 00 Note: Use MOV instruction to write to this register. Write to UARTi bit rate generator when transmission/reception is halted. Transmission enabled ...
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M30245 Group 2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are described below. Figure 2.3.8 shows ...
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M30245 Group Example of wiring Microcomputer Example of operation “1” Receive enable bit (RE) “0” “1” Transmit enable bit (TE) “0” “1” Transmit buffer empty flag (Tl) “0” “H” RTSi “L” CLKi RxDi Transferred from UARTi receive register “1” to ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note: Set the corresponding port direction register to “0”. Setting UARTi transmit/receive control register (i Note: UART2 ...
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M30245 Group Reception enabled b7 b0 UARTi transmit/receive control register 1 UiC1 [Address 03AD 1 1 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled (Note) Writing dummy data (Note Note: Use ...
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M30245 Group 2.3.4 Precautions for Serial I/O (in clock-synchronous serial I/O mode) Transmission/reception (1) With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, ...
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M30245 Group Transmission (1) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if ...
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M30245 Group 2.4 Clock-Asynchronous Serial I/O (UART) 2.4.1 Overview UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of ...
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M30245 Group (2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans- fer rate. The count source for the transfer rate register can be selected from f from the CLK pin. Clocks ...
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M30245 Group (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive ...
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M30245 Group (e) Bus collision detection function This function is to sample the output level of the TxD pin and the input level of the RxD pin; if their values are different, then an interrupt request occurs. The following examples ...
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M30245 Group (8) Registers related to the serial I/O Figure 2.4.2 shows the memory map of serial I/O-related registers, and Figures 2.4.3 to 2.4.6 show UARTi-related registers. 0042 16 UART2 receive/ACK interrupt control register (S2RIC) 0043 16 UART1/3 Bus collision ...
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M30245 Group UARTi transmit buffer register ( (Note) b15 b8 (b7) (b0 UARTi receive buffer register ( b15 b8 (b7) (b0 Figure 2.4.3. UARTi-related registers (1) Rev.2.00 Oct 16, 2006 ...
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M30245 Group UARTi bit rate generator (o (Note ...
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M30245 Group ...
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M30245 Group Interrupt request cause select register Figure 2.4.6. UARTi-related registers (4) Rev.2.00 Oct 16, 2006 page 63 of 354 REJ09B0340-0200 Symbol Address IFSR 035F , 16 Bit Symbol Bit name INT0 ...
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M30245 Group 2.4.2 Operation of Serial I/O (transmission in UART mode) In transmitting data in UART mode, choose functions from those listed in Table 2.4.4. Operations of the circled items are described below. Figure 2.4.7 shows the operation timing, and ...
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M30245 Group Example of wiring Microcomputer Note: Since T Example of operation Transfer clock (1) Transmission enabled (2) Confirme CTS (3) Start transmission “1” Transmit enable bit (TE) “0” Data is set in UARTi transmit buffer register “1” Transmit buffer ...
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M30245 Group Setting UARTi transmit/receive mode register (i Setting UARTi transmit/receive control register 0 (i Note 1: Set the corresponding port direction ...
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M30245 Group Setting UARTi bit rate generator ( UARTi bit rate generator [Address 03A9 UiBRG ( Can be set to 00 Note: Use MOV instruction to write to this register. ...
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M30245 Group 2.4.3 Operation of Serial I/O (reception in UART mode) In receiving data in UART mode, choose functions from those listed in Table 2.4.5. Operations of the circled items are described below. Figure 2.4.10 shows the operation timing, and ...
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M30245 Group Example of wiring Microcomputer Example of operation (1) Reception enabled (2) Start reception BRGi's count source Receive enable “1” bit “0” RxD i Transfer clock Reception started when transfer clock is generated by falling edge Receive of start ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note: Set the RxDi pin's port direction register to “0” when receiving. Setting UARTi transmit/receive control register 0 (i ...
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M30245 Group Setting UARTi bit rate generator ( UARTi bit rate generator [Address 03A9 UiBRG ( Can be set to 00 Note: Use MOV instruction to write to this register. ...
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M30245 Group 2.4.4 Serial I/O Precautions (UART Mode) Description When the level of the CLKi and CTSi pins goes to “H” (Note 1), if the UiMR register is set to any of the following, the UiERE bit in the UiC1 ...
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M30245 Group 2.4.5 Operation of Serial I/O (transmission used for SIM interface) In transmitting data in UARTi (i mode (used for SIM interface), choose functions from those listed in Table 2.4.6. Operations of the circled items are described ...
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M30245 Group Example of wiring Note1: TxDi pin is N-channel open drain and needs a pull-up resistance. Note2: i Example of operation (when direct format ...
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M30245 Group Setting UARTi transmit/receive mode register (i Setting UARTi transmit/receive control register 0 (i Setting UART transmit/receive control register 1 (i=0 ...
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M30245 Group Setting UARTi bit rate generator ( UARTi bit rate generator [Address 03A9 UiBRG ( Can be set to 00 Note: Use MOV instruction to write to this register. ...
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M30245 Group 2.4.6 Operation of Serial I/O (reception used for SIM interface) In receiving data in UARTi (i mode (used for SIM interface), choose functions from those listed in Table 2.4.7. Operations of the circled items are described ...
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M30245 Group Example of wiring Microcomputer Note1: TxDi pin is N-channel open drain and needs a pull-up resistance. Note2: i Example of operation (when inversed format ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note 1: Set the RxDi pin's port direction register to “0” when receiving. 2: Set the corresponding port direction register to ...
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M30245 Group Setting UARTi bit rate generator ( UARTi bit rate generator [Address 03A9 UiBRG ( Can be set to 00 Note: Use MOV instruction to write to this register. ...
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M30245 Group 2.4.7 Clock Signals in used for the SIM Interface In conforming to the SIM interface, the UART clock signal within the SIM card needs to conform to the UARTi (i clock signal within the microprocessor. Two ...
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M30245 Group Clock generator X IN Timer Aj counter Timer Ak counter f 1 Figure 2.4.19. Example of connection Rev.2.00 Oct 16, 2006 page 82 of 354 REJ09B0340-0200 M30245 TA jOUT flip-flop TA kOUT flip-flop External clock CLKi Bit rate ...
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M30245 Group Table 2.4.8. UARTi bit rate adjustment factor (i SIM card Bit rate internal clock D F(Hz) 372 1/2 1/4 1/8 1/16 1/32 1/64 558 ...
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M30245 Group Table 2.4.9. TimerAi register adjustment factor SIM card Bit rate internal clock D F(Hz) 372 1/2 1/4 1/8 1/16 1/32 1/64 558 1/2 1/4 1/8 1/16 ...
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M30245 Group 2.5 Serial Interface Special Function 2.5.1 Overview Serial interface special function can control communications on the serial bus using SSi input pins. The following is an overview of the serial interface special function. (1) Transmission/reception format 8-bit data ...
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M30245 Group Following are some examples in which various functions (a) through (c) are selected: • Transmission Operation WITH: outputting transmission data at falling edge of transfer clock, no clock delay, master mode • Reception Operation WITH: inputting reception data ...
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M30245 Group 0042 16 UART2 receive/ACK interrupt control register (S2RIC) 0043 16 UART1/3 Bus collision interrupt control register (S13BCNIC) 0048 16 UART1 receive/ACK/SSI1 interrupt control register (S1RIC) 0049 16 UART0/2 Bus collision interrupt control register (S02BCNIC) 004A 16 UART0 receive/ACK/SSI0 ...
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M30245 Group UARTi transmit buffer register ( (Note) b15 b8 (b7) (b0 UARTi receive buffer register ( b15 b8 (b7) (b0 Figure 2.5.2. Serial interface special function-related registers (1) Rev.2.00 ...
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M30245 Group UARTi bit rate generator (o (Note ...
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M30245 Group ...
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M30245 Group UARTi special mode register 1 ( UARTi special mode register 2 ( Figure 2.5.5. Serial interface special function-related ...
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M30245 Group UARTi special mode register 3 ( Figure 2.5.6. Serial interface special function-related registers (5) Rev.2.00 Oct 16, 2006 page 92 of 354 REJ09B0340-0200 b1 b0 Symbol Address UiSMR3 (i=0 ...
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M30245 Group UARTi special mode register 4 ( Interrupt request cause select register Figure 2.5.7. Serial interface special function-related registers (6) Rev.2.00 Oct ...
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M30245 Group 2.5.2 Operation of Serial Interface Special Function (transmission in master mode without delay) In transmitting data in serial interface special function master mode, choose functions from those listed in Table 2.5.1. Operations of the circled items are described ...
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M30245 Group Example of wiring Microcomputer Example of operation (1) Output "L" at the receiver side IC (2) Transmission enabled (3) Start transmission Tc Transfer clock “H” Port “L” “1” Transmit enable bit (TE) “0” Data is set to UARTi ...
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M30245 Group Setting UARTi transmit/receive mode register (i Setting UARTi transmit/receive control register 0 (i Note 1: Set the corresponding port direction register to “0”. ...
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M30245 Group Setting UARTi transmit/receive control register 1 (i Setting UARTi bit rate generator ( Note: Use MOV instruction to write to this register. Write to UARTi ...
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M30245 Group 2.5.3 Operation of Serial Interface Special Function (reception in master mode with clock delay) In receiving data in serial interface special function master mode, choose functions from those listed in Table 2.5.2. Operations of the circled items are ...
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M30245 Group Example of wiring Microcomputer Example of operation (1) Output "L" on the transmitter side IC (2) Reception enabled (3) Start reception Transfer clock “H” Port “L” “1” Receive enable “0” bit (RE) “1” Transmit enable bit (TE) “0” ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note: Set the RxDi pin's port direction register to “0” when receiving. Setting UARTi transmit/receive control register (i ...
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M30245 Group Setting UARTi transmit/receive control register 1 (i UARTi transmit interrupt cause select bit UARTi continuous receive mode enable bit Data logic select bit Set to “0” in clock synchronous serial ...
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M30245 Group 2.5.4 Operation of Serial Interface Special Function (transmission in slave mode without delay) In transmitting data in serial interface special function slave mode, choose functions from those listed in Table 2.5.3. Operations of the circled items are described ...
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M30245 Group Example of wiring Microcomputer Example of operation (1) Set SSi port to "L" with the output from the receiver side IC port (2) Transmission enabled “1” Transfer clock “0” (TE) “1” Transmit buffer empty flag (TI) “0” “H” ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note: Set the corresponding port direction register to “0”. Setting UARTi transmit/receive control register (i Note 1: ...
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M30245 Group Setting UARTi transmit/receive control register 1 (i UARTi transmit/receive control register 1 UiC1 [Address 03AD UARTi transmit interrupt cause select bit 0 : Transmit buffer empty ( Data logic ...
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M30245 Group 2.5.5 Operation of Serial Interface Special Function (reception in slave mode with clock delay) In receiving data in serial interface special function slave mode, choose functions from those listed in Table 2.5.4. Operations of the circled items are ...
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M30245 Group Example of wiring Microcomputer Example of operation (1) Set SSi port to "L" by the output from the transmitter side IC port (2) Reception enabled “1” Receive enable bit (RE) “0” “1” Transmit enable bit (TE) “0” “1” ...
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M30245 Group Setting UARTi transmit/receive mode register (i Note 1: Set the RxDi pin's port direction register to “0” when receiving. Note 2: Set the corresponding port direction register to “0”. Setting ...
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M30245 Group Setting UARTi transmit/receive control register 1 (i UARTi continuous receive mode enable bit 0 : Continuous receive mode disabled Data logic select bit reverse Set to “0” in ...
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M30245 Group 2.6 Serial sound interface 2.6.1 Overview The Serial Sound Interface (SSI synchronous serial data interface used primary for transferring digital audio data. The bus of the 30245 Serial Sound Interface has four lines: • Continuous serial ...
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M30245 Group (3) LSB/MSB first select function This function is to choose whether to transmit/receive data from bit 1 or bit 7. This is valid when the transfer data length is 8 bits long. Choose either of the following: • ...
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M30245 Group Serial Sound Interface 0 mode register 0 (SS0MR0) 0310 16 0311 Serial Sound Interface 0 mode register 1 (SS0MR1) 16 0312 Reserved 16 0313 Reserved 16 0314 16 Serial Sound Interface 0 transmit buffer register (SS0TXB) 0315 16 ...
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M30245 Group Serial Sound Interface x transmit buffer register (b15) (b8 Note 1: For byte access, write data to addresses 0314 (Do not access to addresses 0315 Serial Sound Interface x receive buffer register (b15) (b8) b0 ...
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M30245 Group Serial Sound Interface x mode register Serial Sound Interface x mode register Figure 2.6.3. Serial Sound Interface ...
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M30245 Group In the case of the USB audio class, the following stream is output. Audio stream (PCM) from the PC to the M30245 USB FIFO For 16-bit data Fifth byte MSB LSB MSB Left Low ...
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M30245 Group 2.6.2 Example of Serial Sound Interface operation When using Serial Sound Interface (SSI), the DMA is recommended for reading and writing data quickly from the receive buffer to the transmit buffer. A programming example using DMA is shown ...
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M30245 Group /***** Serial Sound Interface activation routine for 16 bits *******************************************/ #ifdef OUT_Q_BIT_NO_16 ssi1mr0 = 0x01; ssi1mr0 = 0xf1; ssi1mr1 = 0x21; ssi1mr0 = 0xf7; #endif /***** Serial Sound Interface activation routine for 24 bits ******************************************/ #ifdef OUT_Q_BIT_NO_24 ssi1mr0 ...
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M30245 Group Serial Sound Interface timing (1) WS XMTEN WSDLY = 1 SCK SCKP = 1, WSP = 0 SCKP = 0, WSP = 0 SCKP = 1, WSP = 1 SCKP = 0, WSP = 1 XMTFMT = 0:MSB ...
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M30245 Group Serial Sound Interface timing (3) WS RXEN SCK SCKP = 1, WSP = 0 SCKP = 0, WSP = 0 SCKP = 1, WSP = 1 SCKP = 0, WSP = 1 RFMT1 = 0:MSB first, RFMT1 = ...
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M30245 Group 2.6.3 Precautions for Serial Sound Interface Description For flash memory version SSI transmission data must be latched as the following timing by a receiver. • SCKP=0 (falling edge) : within 3 BCLK cycles from the rising edge of ...
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M30245 Group 2.7 Frequency synthesizer (PLL) This paragraph explains the registers setting method and the notes related to the frequency synthesizer (PLL circuit). 2.7.1 Overview The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and ...
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M30245 Group Frequency Synthesizer Control register Frequency Synthesizer Clock Control register Figure 2.7.3. Frequency synthesizer registers ...
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M30245 Group Frequency Synthesizer Prescaler Register Frequency Synthesizer Multiply Register Frequency Synthesizer Divide Register Figure 2.7.4. ...
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M30245 Group 2.7.2 Operation of frequency synthesizer The following explains how to setup after hardware reset. Table 2.7.1 to 2.7.3 show frequency synthe- sizer related registers setting examples. Operation (1) Cancel the protect register. (2) Set the frequency synthesizer related ...
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M30245 Group Frequency Multiplier f is generated via the Frequency Synthesizer Mul-tiply register (FSM: address 03DD VCO Frequency Multiply register is set to 255, multiplication is disabled and f should be set so that f VCO synthesizer multiply register is ...
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M30245 Group 2.7.3 Precautions for Frequency synthesizer (1) Bits 6 and 5 of frequency synthesizer control register are set to (bit6, bit5)=( reset. When using the frequency synthesizer, we recommended to set to (bit6, bit5)=(1, 0). (2) Set ...
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M30245 Group 2.8 USB function 2.8.1 Overview The USB function control unit of the M30245 group is compliant with USB2.0 specification and supports Full-Speed transfer. USB2.0 specification defines the following four kinds of transfer types: Control Transfer Isochronous Transfer Interrupt ...
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M30245 Group Interrupt Transfer This transfer is used to notify the host of aperiodic and low-frequency data from the device. For example, they include the notification of out of paper in printer and data concerning devices such as the mouse ...
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M30245 Group SOF Packet: Packet to start the frame to be issued from the host for every 1ms. 8 bits PID Frame number CRC5 PID: SOF(0xA5) Token Packet: Packet to be issued from the host at the time of transaction ...
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M30245 Group Transaction A transaction is the unit in which the host CPU schedules one frame. Each transaction is config- ured with packet, and the transaction types are determined according to the configuration pat- tern. The transaction types and formats ...
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M30245 Group Communication Sequence The control transfer is used common to all devices at the time of setup, which consists of three kinds of stages being combined for one processing. The control transfer starts with setup stage. According to the ...
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M30245 Group Control Read Transfer In setup stage, host notifies the device that it is control read transfer. Then, in data stage, data are transmitted from the device to host through repetition of IN transaction. Finally, in status stage, OUT ...
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M30245 Group (3) Bulk Transfer Bulk IN Transfer In bulk IN transfer which data are transmitted from the device to the host CPU, IN transactions are repeated. When transmit data are available in IN FIFO, the M30245 group issues a ...
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M30245 Group (4) Isochronous Transfer Isochronous IN Transfer In isochronous IN transfer which data are transferred from the device to the host CPU, isochronous (IN) transactions are repeated. Isochronous transaction does not have the handshake phase. The data packet consists ...
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M30245 Group (6) Device State The device has states and, transits between the states. The M30245 group does not execute state transition on the hardware. Control it by the software based on requests of the related USB interrupt request. The ...
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M30245 Group Hub Deconfigured USB bus reset detected (USB reset interrupt) Execute SetConfiguration (USB function interrupt) (Configuration Value=0) Figure 2.8.7. Device state transition Rev.2.00 Oct 16, 2006 page 136 of 354 REJ09B0340-0200 Attached state Hub Configured Suspend detected (USB suspend ...
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M30245 Group USB control register (USBC) 000C 16 USB Attach/Detach register (USBAD) 001F 16 USB Endpoint 0 interrupt control register (EP0IC) 0046 16 USB suspend interrupt control register (SUSPIC) 0056 16 USB resume interrupt control register (RSMIC) 0058 16 USB ...
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M30245 Group Table 2.8.2. List of USB Related Registers Items Section name 2.8.2 USB function control 2.8.3 USB Interrupt 2.8.4 USB Operation (Suspend/Resume Function) 2.8.5 USB Operation (Endpoint 0) 2.8.6 USB Operation (Endpoint 1-4 reception) 2.8.7 USB Operation (Endpoint 1-4 ...
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M30245 Group 2.8.2 USB function control The USB function control unit needs to be enabled for using the USB function. The initialization procedure of the USB function control unit is explained below: (1) Related Registers USB control register This register ...
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M30245 Group USB attach/detach register This register is used to control attach/detach from the USB host without physically attaching/detaching the USB cable. •Port 9 -Second bit 0 The port P9 operates as standard port when this bit is set to ...
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M30245 Group USB endpoint enable register Endpoints are used to enable endpoint IN/OUT FIFOs for use. The endpoint 0 is always enabled and cannot be disabled by software. All Endpoints are disabled after reset. ...
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M30245 Group USB endpoint x(x OUT FIFO data register Endpoints respectively have their OUT FIFOs. When data are received from the host PC, read the receive data from these registers. Access these registers in word ...
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M30245 Group (2) Enable of USB Function Control Unit The initialization procedure of the USB function control unit of the M30245 group after hardware reset is explained below. Further, for power supply being supplied from the USB, the total driving ...
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M30245 Group f 12MHz Figure 2.8.15. Setting example of frequency synthesizer division RESET FSE LS USBC5 USBC7 Figure 2.8.16. Setup timing of frequency synthesizer after hardware reset Rev.2.00 Oct 16, 2006 page 144 of 354 REJ09B0340-0200 FSD FSP ...
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M30245 Group Clearing the protect b7 0 Setting frequency synthesizer related registers b7 b7 Setting frequency synthesizer control register Setting the protect Checking the frequency synthesizer locked status bit It ...
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M30245 Group When using main clock SYN USB clock enabled Selecting ATTACH/DETACH USB block enabled (Note ...
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M30245 Group Initialization of endpoint 0 (Control transfer) (b15 Setting the size and start location of IN/OUT FIFO (b15) (b8 (b15) (b8 ...
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M30245 Group Initialization of endpoint x (x (Bulk tranfer/Interrupt transfer/Isochronous transfer) (b15 (b15 (b15 (b15 ...
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M30245 Group (3) Disable of USB Function Control Unit After the USB function control unit being enabled, if the system design requires to disable the USB function, follow the procedure below: 1: Disable the USB clock by clearing USB enable ...
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M30245 Group 2.8.3 USB Interrupt The USB related interrupts include USB suspend interrupt, USB resume interrupt, USB reset interrupt, USB endpoint 0 interrupt, USB function interrupt, and USB SOF interrupt. (1) Related Registers USB function interrupt status register This register ...
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M30245 Group USB Interrupt Status register (Note) (b8) (b15 Figure 2.8.21. USB function interrupt status register USB function interrupt clear register This register is used to clear the USB function ...
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M30245 Group USB Function Interrupt Clear register (b8) (b15 Figure 2.8.22. USB function interrupt clear register USB Function Interrupt Enable register (b8) (b15 ...
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M30245 Group USB frame number register This register is used to contain 11-bit frame number of SOF token received from the host CPU. This is the read-only register. The configuration of USB frame number register is shown in Figure 2.8.24. ...
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M30245 Group (2) USB Endpoint 0 Interrupt In the endpoint 0 interrupt, the interrupt request occurs when the data transmit/receive of endpoint 0 are completed. Set the interrupt priority level by using USB endpoint 0 interrupt control register (EP0IC: address ...
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M30245 Group (3) USB Function Interrupt The USB function interrupts include the endpoint x(x=1~4) IN interrupt, endpoint x(x=1~4) OUT inter- rupt, and error interrupt. An interrupt request occurs on completion of data transmit/receive or on occurrence of an error such ...
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M30245 Group (4) USB Reset Interrupt This interrupt is used for detection of the USB reset. This occurs when the USB function control unit has received reset signal from the host CPU (or detected SE0 on the D+/D- line for ...
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M30245 Group (7) USB SOF (Start of Frame) Interrupt This interrupt is valid to control the isochronous transfer. When a valid SOF PID is detected, receive of an SOF packet is recognized and an interrupt request occurs. The frame number ...
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M30245 Group (8) USB Function Interrupt Routine This interrupt is used to control data flow. This occurs on completion of data transmit/receive or on occurrence of an error such as overrun/underrun. When using the USB function interrupt, set the interrupt ...
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M30245 Group USB function interrupt control register [Address 005D b7 b0 USBFIC 0 Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested USB function interrupt enable register [Address 0288 (b15) (b8 ...
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M30245 Group USB function interrupt request detected USBIS Read one word and store it to RAM RAM Write one word to USBIC RAM,bit8=1? Y USB error interrupt routine RAM,bit1=1 or RAM,bit3=1 or RAM,bit5=1 or RAM,bit7=1 Y USB endpoint x OUT ...
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M30245 Group 2.8.4 USB Operation (Suspend/Resume Function) The USB device has received the suspend signal from the host CPU following the power input state, and then controls power supply and shifts the state into the suspend state. And, by receiving ...
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M30245 Group USB Power Management register (b8) (b15 Figure 2.8.27. USB power management register Rev.2.00 Oct 16, 2006 page 162 of 354 REJ09B0340-0200 b0 Symbol 0 ...
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M30245 Group (2) USB Suspend Function In the M30245 group, the USB suspend status flag (SUSPEND) of USB power management register (address 0282 ) is set to “1” when the suspend signal has been received from the host CPU (or ...
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M30245 Group (3) USB Resume Function Returning Routine from USB Suspend State To return from the USB suspend state, the M30245 group uses the USB resume interrupt occurred by receiving the resume signal from the host or the interrupt for ...
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M30245 Group - Returning Routine of USB Function Control Unit To return from the USB suspend state to the previous state, perform return control of the USB function control unit as follows. Further, clearing the bit of protect register (address ...
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M30245 Group (4) USB Suspend Interrupt Request Processing Routine When using the USB suspend interrupt, set USB suspend interrupt control register (address 0056 In the USB suspend interrupt, when the USB suspend status flag (SUSPEND) of USB power manage- ment ...
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M30245 Group Stop all clocks Insert at least four NOPs following JMP.B instruction after the instruction that sets the all clock stop control bit to Execute the interrupt process for return from suspend ...
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M30245 Group Clearing the protect Setting frequency synthesizer control register Clearing the protect Wait till the frequency synthesizer stabilized Note: Check the ...
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M30245 Group 2.8.5 USB Operation (Endpoint 0) Endpoint 0 is used only for control transfer. Endpoint 0 FIFO consists of total 256 bytes including IN (transmit) FIFO and OUT (receive) FIFO each respectively of 128 bytes. The starting position is ...
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M30245 Group USB Function Address register (b8) (b15 Figure 2.8.31. USB address register USB endpoint 0 control and status register USB endpoint 0 control and status register consists ...
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M30245 Group - Data exceeding the one specified in the SETUP stage are required. (An OUT token is received after the DATA_END flag is set.) - Data exceeding the one specified are received in USB endpoint 0 MAXP register. Except ...
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M30245 Group • SET_DATA_END bit This bit controls setting of the DATA_END flag to “1”. When the last data has been written in IN FIFO in the IN data phase or when the last data has been read from OUT ...
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M30245 Group USB Endpoint 0 Control and Status register (b8) (b15 Figure 2.8.32. USB endpoint 0 control and status register Rev.2.00 Oct 16, 2006 page 173 of 354 REJ09B0340-0200 b0 Address Symbol 0298 EP0CS 16 ...
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M30245 Group USB endpoint 0 MAXP register This register indicates the IN/OUT maximum packet size of endpoint 0. When a GET_DESCRIPTION request is received from the host CPU, write to this register to change the IN/OUT maximum packet size value ...
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M30245 Group (2) Control Transfer: Endpoint 0 Receive The endpoint 0 receives the packet data from the host CPU in the setup stage or the data stage by the control write transfer. When the receive of a valid SETUP packet ...
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M30245 Group (3) Control Transfer: Endpoint 0 Transmit The endpoint 0 transmits the packet data to the host CPU in the data stage by the control read after completion of receive request analysis process in the setup stage. Write one ...
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M30245 Group (4) Control Transfer: Example of Standard Device Request Receive The control transfer includes the setup stage, data stage and status stage. Which one of write transfer, read transfer and no data transfer is executed in the data stage ...
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M30245 Group Confirming of receive data (b15) (b8 Note 1: There is no receive data in FIFO 0 when this bit is set to “0”. Reading of receive data (b15) (b8 Setting of receive ...
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M30245 Group Setting of USB endpoint 0 control and status register (b15 Waiting for completion of status phase (DATA_END flag: 1 Setting of address to USB address register (Note 1) (b15 ...
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M30245 Group Confirming of receive data (b15) (b8 Note 1: There is no receive data in FIFO 0 when this bit is set to “0”. Reading of receive data (b15) (b8 Setting ...
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M30245 Group Setting of USB endpoint 0 control and status reister (Note 1) (b15 Note 1: Set the SET_IN_BUF_RDY bit and the SET_DATA_END bit simultaneously. The USB function control unit is shifted to status stage Figure 2.8.39. ...
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M30245 Group 2.8.6 USB Operation (Endpoints Receive) Endpoints can apply to the isochronous transfer, bulk transfer and interrupt transfer. The endpoints respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs. ...
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M30245 Group (1) Related Registers USB endpoint x(x OUT control and status register •OUT_BUF_STS1, OUT_BUF_STS0 flags These flags indicate OUT FIFO state. At the time of reading the receive data from the host PC, read these flags to ...
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M30245 Group •TOGGLE_INIT bit This bit initializes data toggle sequence bit in bulk/interrupt transfer. With this bit being set to “1”, the PID of the next packet to be received from the host CPU becomes DATA0. When initialization of the ...
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M30245 Group USB Endpoint x OUT Control and Status register (b8) (b15 Figure 2.8.40. USB endpoint x(x OUT control and status register Rev.2.00 Oct 16, 2006 page 185 of 354 REJ09B0340-0200 Address b0 ...
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M30245 Group USB endpoint x(x OUT MAXP register This register indicates endpoint x(x=1~4) OUT maximum packet size. The default value is 0 byte. When the endpoint is initialized due to any reason such as that the request for ...
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M30245 Group USB endpoint x(x OUT FIFO configuration register This register sets endpoint x(x=1~4) OUT FIFO. •BUF_NUM This bit sets the starting location of the endpoint x(x= 1~4) OUT FIFO per 64 bytes. For example, when OUT FIFO ...
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M30245 Group (2) Bulk Transfer: Endpoints Receive Setting of Transfer Type When endpoints OUT are used for bulk transfer, ISO bit of USB endpoint x(x OUT control and status register is set ...
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M30245 Group When an error is detected in bulk OUT transfer, a response is not returned without ACK and NAK responses (Error checks such as CRC check and bit-justification, conforming to USB2.0 specifica- tion, are automatically performed. So the error ...
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M30245 Group (3) Isochronous Transfer: Endpoints Receive Setting of Transfer Type When endpoints OUT are used for isochronous transfer, ISO bit of USB endpoint x(x OUT control and status register is set ...
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M30245 Group (4) Interrupt Transfer: Endpoints Receive Setting of Transfer Type When endpoints OUT are used for interrupt transfer, ISO bit of USB endpoint x(x OUT control and status register is set ...