IDT72104L35J Integrated Device Technology, Inc., IDT72104L35J Datasheet
IDT72104L35J
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IDT72104L35J Summary of contents
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... RT LOGIC / The IDT logo is a registered trademark of Integrated Device Technology,Inc. COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 APPLICATIONS: • High-speed data acquisition systems • ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 DESCRIPTION (CONTINUED) The IDT72103/72104 may be configured to handle serial word widths of four or greater using IDT’s unique Flexishift feature. Flexishift allows serial width and depth expansion without ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with Respect to GND T Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG I DC ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 PIN DESCRIPTION (Continued) Symbol Name I Expansion Out/ O Half-Full Flag AEF Almost-Empty/ O Almost-Full Flag EF+1 Empty+1 Flag O EF Empty Flag O Sl Serial ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 ELECTRICAL CHARACTERISTICS (Commercial 5.0V 10 Symbol Parameter (1) I Input Leakage Current IL (Any Input) (2) I Output Leakage Current OL V ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 ELECTRICAL CHARACTERISTICS (Commercial 5.0V 10 Symbol Parameter f Parallel Shift Frequency S f Serial-Out Shift Frequency SOCP f Serial-In Shift Frequency SICP PARALLEL-OUTPUT MODE ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 ELECTRICAL CHARACTERISTICS (Commercial 5.0V 10 Symbol Parameter DEPTH EXPANSION MODE TIMINGS XO t Read/Write to LOW XOL XO t Read/Write to HIGH XOH ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 GENERAL SIGNAL DESCRIPTION INPUTS: Data Inputs ( The parallel-in mode is selected by connecting the are the data input lines. ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 OUTPUTS: Data Outputs (Q – Data outputs for 9-bit wide data. These output lines are in a high-impedance condition whenever serial output mode is selected ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 PARALLEL TIMINGS AEF, EF+1, EF FF-1, HF WPW 0– Figure 3. Write Operation in Parallel Data In Mode RT ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 NOTES: 1. Data is valid on this edge The Empty Flag is asserted by in the Parallel-Out mode and is specified by t ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 HF RLZ Q 0-8 WRITE TO LAST PHYSICAL W LOCATION R t XOL XO ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 XIS XIR WRITE TO FIRST PHYSICAL LOCATION ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 SERIAL TIMINGS: RS SICP SICP 1-8 NOTE: 1. SICP should be in the steady LOW or HIGH during t RS SOCP SOCP Q 0-8 t NOTE: ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 SICP (3) SI/ SIX NOTES: 1. For the stand alone mode and the input ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 SICP D =W n (1) R NOTES: 1. Parallel Read shown for reference only. Can also use serial output mode. 2. The Empty Flag is ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 SICP W=D n-1 FF NOTES: 1. The Full Flag is asserted in the Serial-ln mode by using the t edge of SICP following a (t ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 HALF-FULL + 1 SICP ALMOST-FULL + 1 AEF AEF Figure 25. Half-Full, Almost-Full and Almost-Empty Timings for Serial-In Mode W HF HALF-FULL (1/2) SOCP AEF ALMOST-EMPTY – ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 OPERATING DESCRIPTION PARALLEL OPERATING MODES: Parallel Data Input SI By setting /PI HIGH, data is written into the FIFO in parallel through the D0-D8 input data lines. Parallel ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 INPUT CONFIGURATION TABLE Parallel Single Pin Input Device SI /PI HIGH LOW Sl HIGH or LOW Input Data SICP HIGH or LOW Input Clock SIX HIGH HIGH W Write ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 DATA IN (D) (W) WRITE (FF) FULL FLAG (RS) RESET (SI/PI NOTE: 1. Flag detection is accomplished by monitoring all the flag signals of either ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 DEPTH EXPANSION (DAISY CHAIN) MODE The IDT72103/4 can be easily adapted to applications where the requirements are for greater than 2048/4096 words. Figure 29 demonstrates Depth Expansion using three ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 BIDIRECTIONAL MODE Applications requiring data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72103/4 as shown in Figure 30. ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 TABLE 3: RESET AND FIRST LOAD TRUTH TABLE — DEPTH EXPANSION/COMPOUND EXPANSION MODE Inputs Mode Reset-First 0 0 Device Retransmit all 0 1 Other Devices ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 SINGLE DEVICE SERIAL INPUT CONFIGURATION SERIAL-IN CLOCK SERIAL-IN DATA SICP ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 SERIAL INPUT WIDTH EXPANSION SERIAL-IN DATA SERIAL-IN CLOCK V CC SICP D OF FIFO #1 8 AND SIX OF FIFO # FIFO # AND OF ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION SERIAL DATA SIX 8 IDT72104 SICP 0 SIX ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 SERIAL-OUT CLOCK SERIAL-OUT DATA SOCP ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 SOCP-SERIAL OUTPUT CLOCK DELAYED R TIMING GENERATOR SO/PO SERIAL-OUTPUT CLOCK V CC SOCP Q OF FIFO #1 8 AND SOX OF FIFO # FIFO #2 6 ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 SERIAL OUTPUT WITH DEPTH EXPANSION SOCP NOTE All /PI pins are tied to VCC and /PO pins are tied to GND ...
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IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 ORDERING INFORMATION IDT XXXXX X XXX Device Power Speed Package Type X X Process/ Temperature Range Blank 72103 72104 5.37 COMMERCIAL TEMPERATURE RANGES Commercial ...