M30620SFP Renesas Electronics Corporation., M30620SFP Datasheet
M30620SFP
Related parts for M30620SFP
M30620SFP Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April ...
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MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY M16C/62 User's manual Group ...
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Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to ...
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... MR0 Function varies with each operation mode MR1 MR2 MR3 TCK0 Count source select bit (Function varies with each operation mode) TCK1 • M30620MC-XXXFP/GP • M30620SFP/GP • M30622MA-XXXFP/GP • M30624MG-XXXFP/GP M30620SFP/GP M30622SFP/GP M30624FGFP/GP M30624FGLFP/GP External ROM version Flash memory version W.....Write O ...
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This manual comprises of eight chapters. Use the suggested chapters as a reference for the following topics understand hardware specifications ................................................... Chapter 1 Hardware * To understand the basic way of using peripheral features and the operation timing ...
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M16C Family-related document list Usages (Microcomputer development flow) Selection of microcomputer Outline design of system Detail design of system Hard- Soft- ware ware devel- devel- opment opment System evaluation M16C Family Line-up M16C Family Type of document Data sheet and ...
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Table of Contents Chapter 1 Hardware ________________________________________ Description ............................................................................................................................................2 Memory ............................................................................................................................................... 11 Central Processing Unit (CPU) ........................................................................................................... 12 Reset ................................................................................................................................................... 15 Memory Space Expansion Features ................................................................................................... 22 Processor Mode .................................................................................................................................. 28 Bus Settings ........................................................................................................................................ 32 Bus Control ......................................................................................................................................... 34 Clock ...
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Overview .............................................................................................................................. 276 2.1.2 Protect Operation ................................................................................................................. 278 2.2 Timer A ....................................................................................................................................... 280 2.2.1 Overview .............................................................................................................................. 280 2.2.2 Operation of Timer A (timer mode) ...................................................................................... 286 2.2.3 Operation of Timer A (timer mode, gate function selected) ................................................. 288 2.2.4 ...
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Clock-Asynchronous Serial I/O (UART) ...................................................................................... 348 2.5.1 Overview ..............................................................................................................................348 2.5.2 Operation of Serial I/O (transmission in UART mode) ......................................................... 358 2.5.3 Operation of Serial I/O (reception in UART mode) .............................................................. 362 2.5.4 Operation of Serial I/O (transmission compliant with ...
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Overview ............................................................................................................................ 424 2.10.2 Operation of CRC Calculation Circuit ................................................................................ 425 2.11 Watchdog Timer ....................................................................................................................... 426 2.11.1 Overview ............................................................................................................................ 426 2.11.2 Operation of Watchdog Timer ............................................................................................ 428 2.12 Address Match Interrupt ........................................................................................................... 430 2.12.1 Overview ............................................................................................................................ 430 2.12.2 Operation ...
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Interrupt Enable Flag ...........................................................................................................493 4.2.2 Interrupt Request Bit ............................................................................................................ 493 4.2.3 Changing the Interrupt Control Register .............................................................................. 494 4.2.4 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) .................... 495 4.3 Interrupt Sequence ..................................................................................................................... 496 4.3.1 Interrupt ...
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Connecting Low-Speed Memory ......................................................................................... 534 5.5.3 Connectable Memories ........................................................................................................ 538 5.6 Releasing an External Bus (HOLD input and HLDA output) ....................................................... 540 5.7 Precautions for External Bus ...................................................................................................... 541 Chapter 6 External ROM Version_____________________________ 6.1 Pin Configuration ........................................................................................................................ 545 ...
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Quick Reference to Pages Classified by Address Address Register 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 (PM0) 0004 16 Processor mode register 1(PM1) 0005 16 System clock control register 0 (CM0) 0006 16 System clock ...
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Quick Reference to Pages Classified by Address Address Register 0340 Timer B3 count start flag (TBSR) 16 0341 16 0342 16 Timer A1-1 register (TA11) 0343 16 0344 16 Timer A2-1 register (TA21) 0345 16 0346 16 Timer ...
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Quick Reference to Pages Classified by Address Address 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 ...
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Chapter 1 Hardware ...
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Description Description The M16C/62 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring ...
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Description Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). PIN CONFIGURATION (top view ...
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Description PIN CONFIGURATION (top view ...
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Description Block Diagram Figure 1.1 block diagram of the M16C/62 group. Block diagram of the M16C/62 group 8 I/O ports Port P0 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) ...
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Description Performance Outline Table 1.1 performance outline of M16C/62 group. Table 1.1.1. Performance outline of M16C/62 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P10 (except P8 Input ...
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... EPROM version (Note) 100P6S-A Flash memory 20K byte 5V version 100P6Q-A 100P6S-A Flash memory 20K byte 3V version 100P6Q-A 100P6S-A 10K byte 100P6Q-A External ROM version 100P6S-A 3K byte 100P6Q-A Mitsubishi microcomputers M16C / 62 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M30620SFP/GP M30622SFP/GP External ROM version November. 1999 Remarks 7 ...
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Description Type No – Figure 1.1.5. Type No., memory size, and package 8 Mitsubishi microcomputers M16C / 62 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package type ...
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Pin Description Pin Description Pin name Signal name Power supply input CNV CNV Input SS SS RESET Reset input Input X Clock input Input IN X Clock output Output OUT BYTE External data Input bus ...
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Pin Description Pin Description Pin name Signal name I/O port P5 Input/output 0 7 Output WRL / WR, Output WRH / BHE, Output RD, Output BCLK, Output HLDA, Input HOLD, ALE, Output RDY Input ...
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Memory Operation of Functional Blocks The M16C/62 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral ...
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CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 ...
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CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction ...
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CPU • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when ...
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Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is ...
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Reset Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. Table 1.6.1. Pin status when RESET ...
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Reset (1) Processor mode register 0 (Note) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Data ...
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Reset (58) Count start flag (59) Clock prescaler reset flag (60) One-shot start flag (61) Trigger select flag (62) Up-down flag (63) Timer A0 mode register (64) Timer A1 mode register (65) Timer A2 mode register (66) Timer A3 mode ...
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SFR 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 (PM0) 0004 16 Processor mode register 1(PM1) 0005 16 System clock control register 0 (CM0) 0006 16 System clock control register 1 (CM1) 0007 16 Chip select ...
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SFR 0340 Timer B3 count start flag (TBSR) 16 0341 16 0342 16 Timer A1-1 register (TA11) 0343 16 0344 16 Timer A2-1 register (TA21) 0345 16 0346 16 Timer A4-1 register (TA41) 0347 16 Three-phase PWM control ...
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SFR 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 ...
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Memory Space Expansion Functions Memory Space Expansion Features Here follows the description of the memory space expansion function. With the processor running in memory expansion mode or in microprocessor mode, the memory space expansion features provide the means of expanding ...
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Memory Space Expansion Functions (2) Expansion mode 1 In this mode, the memory space can be expanded by 176K bytes in addition to that in normal mode. Figure 1.8.2 shows the memory location and chip select area in expansion mode ...
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Memory Space Expansion Functions A connection example Figure 1.8.3 shows a connection example of the MCU with the external memories in expansion mode 1. _______ In this example, CS0 is connected with a 1-M byte flash ROM and CS2 is ...
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Memory Space Expansion Functions (3) Expansion mode 2 In expansion mode 2, the data bank register (0000B register. Data bank register Figure 1.8.4. Data bank register Expansion mode 2 (memory space = ...
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Memory Space Expansion Functions The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The bank selection bits are used to set a bank number for accessing data ...
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Memory Space Expansion Functions Areas used for data only 000000 16 to 380000 16 Area commonly used for data and programs 380000 to 3BFFFF 16 16 Area commonly used for data and programs 3C0000 to 3FFFFF 16 16 Figure 1.8.7. ...
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Software Reset Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 0004 microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) Types ...
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Processor Mode Processor mode register 0 (Note 1) Symbol PM0 Bit symbol PM00 PM01 PM02 PM03 PM04 PM05 PM06 PM07 Note 1: Set bit 1 of the protect register (address 000A Note ...
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Processor Mode Single-chip mode Memory expansion mode 00000 16 SFR area 00400 16 Internal RAM area XXXXX 16 04000 16 Inhibited D0000 16 YYYYY 16 Internal ROM area FFFFF 16 Address XXXXX Type No. M30622M4 00FFF 16 M30620M8 02BFF 16 ...
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Processor Mode Figure 1.10.2 shows the memory maps and the chip selection areas effected by PM13 (the internal re- served area expansion bit) in each processor mode for the product having an internal RAM of more than 15K bytes and ...
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Bus Settings Bus Settings The BYTE pin and bits the processor mode register 0 (address 0004 Table 1.11.1 shows the factors used to change the bus settings. Table 1.11.1. Factors for switching bus settings Bus setting ...
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Bus Settings Table 1.11.2. Pin functions for each processor mode Single-chip Processor mode mode Multiplexed bus space select bit Data bus width BYTE pin level I/O port I/O port ...
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Bus Control Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. ...
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Bus Control Table 1.12.2. External areas specified by the chip select signals (A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes) Memory space Processor mode expansion mode Memory expansion mode ...
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Bus Control (3) Read/write signals With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 0004 _____ ________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an ...
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Bus Control ________ (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure 1.12. “L” is being input to the RDY at the ...
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Bus Control (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of ...
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Bus Control (8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (0004 When set to “1”, the output floating. Note: Before attempting to change the contents of the processor ...
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Bus Control < Separate bus (no wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Separate bus (with wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Multiplexed bus > ...
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Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.13.1. Main clock and sub-clock generating circuits Use of clock Usable oscillator ...
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Clock Generating Circuit Clock Control Figure 1.13.3 shows the block diagram of the clock generating circuit. CM10 “1” Write signal RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM0i : Bit i at address 0006 CM1i : ...
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Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided the ...
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Clock Generating Circuit Figure 1.13.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note Symbol CM0 Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 ...
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Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 output from the P5 /CLK 7 0006 ) is set to “1”, the output of f ...
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Wait Mode Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock ...
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Status Transition Of BCLK Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control registers 0 ...
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Power control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. ...
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Power control Transition of stop mode, wait mode All oscillators stopped Stop mode Interrupt All oscillators stopped Stop mode All oscillators stopped Stop mode Transition of normal mode CM06 = “1” Main clock is oscillating CM04 = “0” Sub clock ...
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Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.13.6 shows the protect register. The values in the processor mode register ...
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Interrupt Overview of Interrupt Type of Interrupts Figure 1.14.1 lists the types of interrupts. Software Interrupt Hardware Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.14.1. Classification of interrupts • Maskable interrupt ...
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Interrupt Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the ...
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Interrupt Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset Reset occurs if an “L” is input to the RESET pin. _______ • ...
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Interrupt Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.14.2 shows ...
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Interrupt • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB ...
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Interrupt Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt ...
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Interrupt Interrupt control register (Note2 Bit symbol Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This ...
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Interrupt Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is ...
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Interrupt Rewrite the interrupt control register To rewrite the interrupt control register point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control ...
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Interrupt Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here interrupt occurs during execution of an ...
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Interrupt Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time ( shown in Table 1.14.5. Table 1.14.5. Time required for executing the interrupt sequence Interrupt ...
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Interrupt Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, ...
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Interrupt The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the ...
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Interrupt Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG was immediately before the start of interrupt sequence and the contents of the ...
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Interrupt Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus ...
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INT Interrupt ______ INT Interrupt ________ ________ INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. Of interrupt control registers, 0048 register, and 0049 is used both ...
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NMI Interrupt ______ NMI Interrupt ______ An NMI interrupt is generated when the input to the non-maskable external interrupt. The pin level can be checked in the port P8 03F0 ). 16 This pin cannot be ...
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Address Match Interrupt Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled ...
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Precautions for Interrupts Precautions for Interrupts (1) Reading address 00000 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt ...
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Precautions for Interrupts Figure 1.14.13. Switching condition of INT interrupt request (5) Rewrite the interrupt control register • To rewrite the interrupt control register point that does not generate the interrupt request for that register. If ...
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Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog ...
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Watchdog Timer Watchdog timer control register Watchdog timer start register b7 Figure 1.15.2. Watchdog timer control and start registers 72 Symbol Address WDC 000F 16 Bit symbol Bit name High-order ...
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DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right ...
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DMAC Table 1.16.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred DMA request factors (Note) Channel priority Transfer unit Transfer address direction Transfer mode DMA interrupt request generation timing When an underflow occurs in ...
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DMAC DMA0 request cause select register Figure 1.16.2. DMAC register (1) Symbol Address b0 DM0SL 03B8 16 Bit name Bit symbol DMA request cause DSEL0 ...
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DMAC DMA1 request cause select register Bit symbol DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to ...
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DMAC DMAi source pointer ( (b19) (b16)(b15) (b23 DMAi destination pointer ( (b19) (b16) (b15) (b23 DMAi transfer counter ( (b15) (b8) b7 ...
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DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to ...
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DMAC (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) 16-bit transfers and the source address is odd Transferring 16-bit data ...
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DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.16.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of ...
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DMAC DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one ...
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DMAC (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA ...
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Timer Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 1.17.1 and 1.17.2 show the block diagram of timers 1/8 ...
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Timer C32 Noise TB0 IN filter Noise TB1 IN filter Noise TB2 IN filter Noise TB3 IN filter Noise TB4 IN filter Noise TB5 IN filter Note 1: The TB5 ...
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Timer A Timer A Figure 1.17.3 shows the block diagram of timer A. Figures 1.17.4 to 1.17.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai ...
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Timer A Timer Ai register (Note) (b15) (b8 Count start flag Up/down flag Figure 1.17.5. Timer A-related registers (2) 86 Symbol Address TA0 ...
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Timer A One-shot start flag Nothing is assigned attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: Set the corresponding port ...
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Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.1.) Figure 1.17.7 shows the timer Ai mode register in timer mode. Table 1.17.1. Specifications of timer mode Item Count source f ...
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Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and ...
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Timer A Table 1.17.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source • Two-phase pulse signals input to TAi Count operation • Up count or down count can ...
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Timer A Timer Ai mode register (When not using two-phase pulse signal processing Bit symbol Note 1: The settings of the corresponding port register and port direction register are ...
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Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.17.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.17.10 shows the timer Ai mode register ...
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Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit ...
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Timer A Condition : Reload register = 0003 (rising edge of TA Count source “H” TA pin iIN input signal “L” “H” PWM pulse output from TA pin iOUT “L” Timer Ai interrupt “1” request bit “0” Frequency ...
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Timer B Timer B Figure 1.17.14 shows the block diagram of timer B. Figures 1.17.15 and 1.17.16 show the timer B-related registers. Use the timer Bi mode register ( bits 0 and 1 to choose the ...
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Timer B Timer Bi register (Note) (b15) (b8 • Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a ...
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Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.6.) Figure 1.17.17 shows the timer Bi mode register in timer mode. Table 1.17.6. Timer specifications in timer mode Item Count source ...
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Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.17.7.) Figure 1.17.18 shows the timer Bi mode register in event counter mode. Table 1.17.7. Timer specifications in ...
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Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.17.8.) Figure 1.17.19 shows the timer Bi mode register in pulse period/pulse width measurement ...
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Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches “0000 ” 16 “1” Count start flag “0” “1” Timer ...
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Timers’ functions for three-phase motor control Timers’ functions for three-phase motor control Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 1.18.1 to 1.18.3 show registers related to ...
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Timers’ functions for three-phase motor control Three-phase output buffer register 0 (Note Bit Symbol DUB0 DVB0 DW0 DWB0 Nothing is assigned attempt to write to these bits, write “0”. The ...
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Timers’ functions for three-phase motor control Timer Ai register (Note) (b15) (b8 Note: Read and write data in 16-bit units. Timer Ai-1 register (Note) (b15) (b8 Note: Read and write data in 16-bit units. ...
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Timers’ functions for three-phase motor control Three-phase motor driving waveform output mode (three-phase waveform mode) Setting “1” in the mode select bit (bit 2 at 0348 mode that uses four timers A1, A2, A4, and selected. As ...
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Timers’ functions for three-phase motor control Figure 1.18.5 shows the block diagram for three-phase waveform mode. In three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U phase, V ___ phase, and W ...
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Timers’ functions for three-phase motor control Figure 1.18.5. Block diagram for three-phase waveform mode 106 Mitsubishi microcomputers M16C / 62 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ...
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Timers’ functions for three-phase motor control Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6 at 0348 ). Also, set “1” in the timers A4-1, A1-1, A2-1 ...
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Timers’ functions for three-phase motor control phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn’t lap over that of the ...
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Timers’ functions for three-phase motor control Assigning certain values to DU0 (bit 0 at 034A and DUB1 (bit 1 at 034B ) allows the user to output the waveforms as shown in Figure 1.18.7, that is output the ...
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Timers’ functions for three-phase motor control Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit 6 at 0348 ). Also, set “0” in the timers A4-1, A1-1, and A2-1 ...
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Timers’ functions for three-phase motor control A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m U phase output signal U phase output signal ...
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Timers’ functions for three-phase motor control A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurres. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m ...
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Serial I/O Serial I/O Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently ...
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Serial I/O (UART0) RxD 0 Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity CLK 0 reversing circuit CTS/RTS selected CTS / RTS 0 0 Vcc CTS0 from ...
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Serial I/O 1SP SP SP PAR RxDi 2SP PAR 2SP enabled SP SP PAR 1SP Figure 1.19.2. Block diagram of UARTi ( transmit/receive unit Clock synchronous type UART (7 bits) UART (8 bits) Clock ...
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Serial I/O No reverse RxD data RxD2 reverse circuit Reverse 1SP SP SP PAR 2SP PAR enabled 2SP SP SP PAR 1SP PAR disabled Figure 1.19.3. Block diagram of UART2 transmit/receive unit 116 Clock synchronous type UART ...
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Serial I/O UARTi transmit buffer register (b15) (b8 UARTi receive buffer register (b8) (b15 UARTi bit rate generator b7 b0 Figure 1.19.4. Serial I/O-related registers (1) Symbol Address When reset U0TB 03A3 , 03A2 ...
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Serial I/O UARTi transmit/receive mode register Symbol UiMR(i=0,1) Bit symbol SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR STPS PRY PRYE SLEP Note : Set the corresponding port direction register to ...
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Serial I/O UARTi transmit/receive control register UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS TXEPT CRD NCH CKPOL UFORM Transfer format select bit Note 1: Set the corresponding port direction register to “0”. ...
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Serial I/O UARTi transmit/receive control register Symbol UiC1(i=0,1) Bit symbol Nothing is assigned attempt to write to these bits, write “0”. The value, if read, ...
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Serial I/O UART transmit/receive control register Symbol Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP Nothing is assigned attempt to write to this bit, write “0”. The value, ...
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Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.19.2 and 1.19.3 list the specifications of the clock synchronous serial I/O mode. ...
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Clock synchronous serial I/O mode Table 1.19.4. Specifications of clock synchronous serial I/O mode (2) Item Select function • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be ...
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Clock synchronous serial I/O mode UARTi transmit/receive mode registers UART2 transmit/receive mode register Figure 1.19.9. UARTi ...
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Clock synchronous serial I/O mode Table 1.19.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ _______ RTS ...
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Clock synchronous serial I/O mode • Example of transmit timing (when internal clock is selected) Transfer clock “1” Transmit enable “0” Data is set in UARTi transmit buffer register bit (TE) “1” Transmit buffer empty flag (Tl) “0” “H” CTSi ...
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Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 1.19.11, the CLK polarity select bit (bit 6 at addresses 03A4 allows selection of the polarity of the transfer clock. • When CLK polarity select bit = ...
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Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS ...
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Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.19.5 and 1.19.6 list the specifications of the ...
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Clock asynchronous serial I/O (UART) mode Table 1.19.6. Specifications of UART Mode (2) Item Select function • Separate CTS/RTS pins (UART0) UART0 CTS and RTS pins each can be assigned to separate pins • Sleep mode selection (UART0, UART1) This ...
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Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers Bit symbol Note : Set the corresponding port direction register to “0”. UART2 transmit / receive mode register b7 b6 ...
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Clock asynchronous serial I/O (UART) mode Table 1.19.7 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when ...
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Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty flag(TI) “0” “H” CTSi “L” Start ...
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Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” Transmit enable bit(TE) Data is set in UART2 transmit buffer register “0” Transmit buffer ...
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Clock asynchronous serial I/O (UART) mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source “1” Receive enable bit “0” RxDi Transfer clock Reception triggered when transfer clock “1” ...
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Clock asynchronous serial I/O (UART) mode (c) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D transmission buffer register or reading the reception buffer register. Figure 1.19.20 shows the ex- ample ...
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Clock asynchronous serial I/O (UART) mode (3) Clock-asynchronous serial I/O mode (used for the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial ...
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Clock asynchronous serial I/O (UART) mode Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty flag(TI) “0” Start bit TxD RxD 2 Signal conductor level (Note 2) Transmit register “1” empty ...
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Clock asynchronous serial I/O (UART) mode (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D level from the TxD pin when a parity error is detected. In step with ...
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Clock asynchronous serial I/O (UART) mode Figure 1.19.25 shows the example of connecting the SIM interface. Connect T pull-up. Figure 1.19.25. Connecting the SIM interface 140 Microcomputer TxD 2 RxD 2 Mitsubishi microcomputers M16C / 62 Group SINGLE-CHIP 16-BIT CMOS ...
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UART2 Special Mode Register UART2 Special Mode Register The UART2 special mode register (address 0377 Figure 1.19.26 shows the UART2 special mode register. UART2 special mode register Bit symbol IICM ABC ...
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UART2 Special Mode Register In the first place, the control bits related to the I Bit 0 of the UART special mode register (0377 2 Setting “1” in the I C mode select bit (bit 0) goes the circuit to ...
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UART2 Special Mode Register The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the ...
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UART2 Special Mode Register Some other functions added are explained here. Figure 1.19.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt ...
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UART2 Special Mode Register 2 UART2 Special Mode Register 2 UART2 special mode register 2 (address 0376 1.19.29 shows the UART2 special mode register 2. UART2 special mode register Bit symbol ...
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UART2 Special Mode Register 2 Bit 0 of the UART2 special mode register 2 (address 0376 Table 1.19.10 shows the types of control to be changed by I selection bit is set to “1”. Table 1.19.11 shows the timing characteristics ...
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UART2 Special Mode Register 2 P7 /TXD /SDA 0 2 Selector UART2 Noize Filter Start condition detection Stop condition detection Falling edge detection P7 /RXD /SCL 1 2 Selector IICM=1 Noize Filter Noize Filter IICM=0 P7 /CLK 2 2 Selector ...
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UART2 Special Mode Register 2 Bit 4 of the UART2 special mode register 2 (address 0376 Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, ...
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S I/O3 I/O3 I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. Figure 1.19.31 shows the S I/O3, 4 block diagram, and Figure 1.19.32 shows the S I/O3, 4 control register. Table 1.19.12 shows the specifications ...
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S I/O3 I/Oi control register ( (Note Bit symbol SMi0 SMi1 SMi2 SMi3 Nothing is assigned attempt to write to this bit, write “0”. ...
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S I/O3, 4 Table 1.19.12. Specifications of S I/O3, 4 Item • Transfer data length: 8 bits Transfer data format • With the internal clock selected (bit 6 of 0362 Transfer clock f8/2(ni+1), f32/2(ni+1) (Note 1) • With the external ...
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S I/O3, 4 Functions for setting an S When using an external clock for the transfer clock, the S time can be set to the high or the low state. Figure 1.19.33 shows the timing chart for setting an S ...
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A-D Converter A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 , these pins for A-D conversion must therefore be set to input. ...
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A-D Converter f AD 1/2 V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register Addresses (03C1 , 03C0 ) A-D register 0(16 (03C3 , 03C2 ) 16 16 A-D register 1(16) (03C5 , 03C4 ) A-D ...
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A-D Converter A-D control register 0 (Note Bit symbol ADST CKS0 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is Note 2: When changing ...
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A-D Converter A-D control register 2 (Note Bit symbol Reserved bit Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns ...
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A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- sion. Table 1.20.2 shows the specifications of one-shot mode. Figure 1.20.4 shows the A-D control regis- ...
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A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.20.3 shows the specifications of repeat mode. Figure 1.20.5 shows the A-D control register in ...
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A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.20.4 shows the specifications of single sweep mode. Figure 1.20.6 shows the A-D ...
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A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.20.5 shows the specifications of repeat sweep mode 0. Figure ...
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A-D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.20.6 shows the specifications of ...
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A-D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 sample and hold is selected, the rate of conversion of each pin increases result, a ...
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D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 ...
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D-A Converter D-A control register Bit symbol DA0E DA1E Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to be “0” D-A ...
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CRC CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT (X The CRC code is a 16-bit code generated for a block of a ...
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CRC b15 (1) Setting 0000 16 (2) Setting 01 16 b15 The code resulting from sending 1), becomes the remainder resulting from dividing (1000 0000) X conformity with the modulo-2 ...
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Programmable I/O Port Programmable I/O Ports There are 87 programmable I/O ports P10 (excluding P8 input or output using the direction register. A pull-up resistance for each block of 4 ports can be set input-only port ...
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Programmable I/O Port Data bus ...
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Programmable I/O Port Data bus Input to respective peripheral functions Data bus Input to respective peripheral functions Direction ...
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Programmable I/O Port P10 to P10 0 3 (inside dotted-line not included) P10 to P10 4 7 (inside dotted-line included) Data bus Data bus P9 6 Data bus P9 5 Data bus Input to respective ...
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Programmable I/O Port P8 7 Data bus Direction register P8 6 Data bus Note : Do not apply a voltage higher than Vcc to each port. Figure 1.23.4. Programmable I/O ports (4) BYTE BYTE signal input CNV SS CNV signal ...
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Programmable I/O Port Port Pi direction register (Note PDi ( 10, except 8) Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Note: Set bit 2 of protect ...
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Programmable I/O Port Port Pi register 10, except 8) Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Note : Since P7 Port P8 register b7 ...
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Programmable I/O Port Pull-up control register Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Pull-up control register Bit symbol PU10 ...
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Programmable I/O Port Port control register PCR0 Figure 1.23.9. Port control register Symbpl Address When reset PCR 03FF 16 Bit symbol Bit name Port P1 control register 0 : When input port, ...
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Programmable I/O Port Table 1.23.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding (Note) OUT NMI BYTE SS REF Note: With external clock ...
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Usage precaution Usage Precaution Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets ...
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Usage precaution Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is ...
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Usage precaution (4) External interrupt • When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the ...
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Usage precaution External ROM version The external ROM version is operated only in microprocessor mode sure to perform the following: • Connect CNVss pin to Vcc. • Fix the processor mode bit to “11 Built-in PROM version (1) ...
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Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data : EPROMs or floppy disks *: In the case of ...
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Electrical characteristics Table 1.26.1. Absolute maximum ratings Symbol Parameter Supply voltage Vcc Analog supply voltage AVcc Input RESET, voltage ...
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Electrical characteristics Table 1.26.2. Recommended operating conditions (referenced – 40 Symbol Vcc Supply voltage AVcc Analog supply voltage Vss Supply voltage AVss Analog supply voltage HIGH input ...
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Electrical characteristics (Vcc = 5V) Table 1.26.3. Electrical characteristics (referenced to V 16MH unless otherwise specified ...
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Electrical characteristics (Vcc = 5V) Table 1.26.4. A-D conversion characteristics (referenced f(X IN Symbol Parameter Resolution Absolute Sample & hold function not available accuracy Sample & hold function available(10bit) Sample & hold ...