CY7C9689-AC Cypress Semiconductor Corporation., CY7C9689-AC Datasheet
CY7C9689-AC
Specifications of CY7C9689-AC
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CY7C9689-AC Summary of contents
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... The receive section of the CY7C9689 HOTLink accepts a se- rial bit-stream from one of two PECL compatible differential line receivers and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction ...
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... CY7C9689 TAXI HOTLink Transceiver Logic Block Diagram TXDATA/TXCMD CONTROL TX STATUS 13 3 Output Register Input Register Flags Transmit FIFO MUX Pipeline Register BIST LFSR 4B/5B, 5B/6B Encoder MUX Serial Shifter DLB OUTA RXDATA/RXCMD TXCLK RX MODE STATUS REFCLK Mode Output Register Control Flags Receive ...
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... TXDATA[0] 22 RXCMD[1] 23 RXMODE[1] 24 RXMODE[ CY7C9689 CY7C9689 SPDSEL 74 RANGESEL 73 RFEN 72 TXFULL TXHALF 69 RXEN 68 TXCLK 67 RXRST RXSC ...
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... HIGH, the information on TXCMD[1:0] is captured as one of four possible COM- MANDs, and the information on the TXDATA[9:0] bits are ignored. If TXSC/D is LOW, the information on TXDATA[9:0] is captured as one of 1024 possible 10- bit DATA values, and the information on the TXCMD[1:0] bus is ignored. When the encoder is bypassed (ENCBYP is LOW) TXSC/D is ignored 4 CY7C9689 ...
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... LOW, TXFULL toggles at the character rate to provide a character rate reference control-indication since REFCLK is operating at twice of the data rate. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When EXTFIFO is HIGH, TXFULL is active HIGH. 5 CY7C9689 ...
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... RXDATA[7:0] outputs. When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change on the rising edge of the RXCLK output. When the Receive FIFO is enabled (FIFOBYP is HIGH), these outputs change on the rising edge of RXCLK input. RXEN is the three-state control for RXDATA[7:0]. 6 CY7C9689 ...
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... RXCMD[1:0] contains a new COMMAND and the DATA on the RXDATA[9:0] remain unchanged. If RXSC/D is LOW, RXDATA[9:0] contains a new DATA char- acter and the COMMAND output on RXCMD[1:0] remain unchanged. When the decoder is bypassed (ENCBYP is LOW) RXSC/D is not used and may be left unconnected. RXEN is a three-state control for RXSC/D. 7 CY7C9689 ...
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... JK sync character (if BYTE8/10 is HIGH) or the 12-bit LM sync character (if BYTE8/10 is LOW). Framing is disabled when RFEN is LOW. The deassertion of RFEN freezes the character boundary relationship between the serial stream and character clock. RFEN is an asynchronous input, sampled by the internal Receive PLL character clock. 8 CY7C9689 ...
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... RXCMD output pins. When the Receive FIFO is bypassed (FIFOBYP is LOW), RXEMPTY is deasserted whenever data is ready. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, RXEMPTY is active LOW. When EXTFIFO is HIGH, RXEMPTY is active HIGH. 9 CY7C9689 ...
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... Speed Select. Used to select from one of two operating serial rates for the CY7C9689. When SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When LOW, the signaling rate is between 50 and 100 MBaud. Used in combination with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers ...
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... When asserted, both the encoder and decoder are bypassed. Data is transmit- ted without 4B/5B or 5B/6B encoding (but with NRZI encoding), LSB first. Re- ceived data are presented as parallel characters to the parallel interface without decoding. When deasserted, data is passed through both the encoder in the Transmit path and the decoder in the Receive path. 11 CY7C9689 ...
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... Test Mode Select. Used to force the part into a diagnostic test mode used for factory ATE test. This input must be tied HIGH during normal operation. Power for PECL-compatible I/O signals and internal circuits. Ground for PECL-compatible I/O signals and internal circuits. 12 CY7C9689 . DD ...
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... The CY7C9689 offers a large feature set, allowing used in a wide range of host systems. Some of the of configuration options are • ...
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... FIFO flags with either HIGH or LOW status indication Oscillator Speed Selection The CY7C9689 is designed to operate over a two-octave range of serial signaling rates, covering the 50- to 200-MBaud range. To cover this wide range, the PLLs are configured into various sub-regions using the SPDSEL and RANGESEL in- puts, and to a limited extent the BYTE8/10 input ...
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... This 4B/5B encoding scheme “1” EXTFIFO is compliant with the ANSI X3T9.5 (FDDI) committee’s 4B/5B code. The CY7C9689 also contains a 5B/6B encoder that ac- cepts 10-bit data characters and converts these into 12-bit transmission characters. 15 CY7C9689 ...
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... The clock multiplier PLL can accept a REFCLK input between 8 MHz and 40 MHz, however, this clock range is limited by the operation mode of the CY7C9689 as selected by the SPDSEL O UTA and RANGESEL inputs, and to a limited extent, by the BYTE8/10 and FIFOBYP signals. The operating serial signal- ...
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... LFI indication is detected, external logic can toggle selec- tion of the INA± and INB± inputs through the A/B input. When a port switch takes place necessary for the PLL to re- acquire the new serial stream and frame to the incoming char- acters. 17 CY7C9689 > 200 mV, or 400 mV peak-to-peak DIF ...
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... (when BYTE8/10 is LOW) character. If RFEN is LOW, the framer is disabled and no changes are made to character boundaries. The framer in the CY7C9689 operates by shifting the internal character position to align with the character clock. This en- sures that the recovered clock does not contain any significant ...
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... CY7C9689 TAXI HOTLink BIST Sequence D.00 C.JK C.IH C.SR C.SS C.JK C.IH C.QI D.EE C.RR D.B3 C.TR C.SR C.SS C.QQ D.F8 D.89 D.42 C.HI D.94 C.TT D.15 D.0C C.JK C.RS D.CD D.A8 C.TT C.QH D.D4 C.TS D.99 D.46 C.HI D.96 C.HQ D.AE D.D1 D.64 C.II C.IH C.QI C.SS C.QQ D.F0 C.TS C.TR C.QQ D.FC C.TS C.QH D.D3 D.50 C.II C.IH C.SR C.QQ D.FD D.DD D.6E C.HI D.93 D.45 C.TR C.SR C.QQ D.F6 C.RR D.BA D.17 D.0D D.0A C.HH D.85 D.BD D.5E C.HI D.9F D.4F C.HI D.92 C.HQ D.AC C.TT C.SS C.SS C.QQ D.F1 D.74 C.TR C.QI D.E9 D.72 C.HI D.02 C.HH D.84 C.TT C.TR C.HH D.8A C.HQ D.A5 D.58 D.14 C.JK C.IH C.QI D.EF C.TR C.SR C.SS C.QQ D.F9 D.4D D.2A C.HH D.81 D.40 C.HQ D.AF D.5B D.27 D.19 C.SR C.SS C.SS C.QQ D.F2 D.18 C.JK C.RS D.CE C.RR D.B7 C.SS C.QQ D.F3 D.75 D.3C C.QH D.DB D.67 D.39 D.16 C.TR C.QI D.E8 C.TS C.QH D.D0 D.30 C.JK C.IH C.SR C.QQ D.FE D.4C C.II C.RS D.C9 D.62 D.43 D.21 D.10 C.JK C.IH Table 5. Receiver Discard Policies Policy # Policy Description 0 (00) Keep all received characters 1 (01) Process Commands, discard all but the last SYNC character 2 (1X) Process Commands, discard all C5.0 characters C.QQ D.FB D.77 D.3D D.1E D.55 D.2C C.JK C.RS C.TS C.QH D.D2 C.RR D.BC C.TR C.QI D.EB D.73 D.35 D.6A C.HI D.91 D.44 C.II C.TR C.QI D.E3 D.71 D.34 C.HQ D.A3 D.51 D.24 D.E4 C.RR C.TR C.QI D.E0 C.SR C.QQ D.F4 C.TS C.TR D.65 D.38 C.JK C.RS D.C6 D.7E C.HI D.9B D.47 D.28 C.JK C.RS D.C4 C.TS C.HQ D.A9 D.52 C.HI D.48 C.II C.RS D.C8 C.TS D.2B D.13 D.05 D.08 C.JK C.QH D.D5 D.6C C.II C.RS C.II C.IH C.QI D.E5 D.78 D.98 C.TT C.QH D.DE C.RR D.BF C.QI D.EA C.RR D.B1 D.54 C.II C.RS D.CA C.RR D.B5 D.7B D.37 D.1D D.0E C.HH D.87 D.76 C.HI D.9A C.HQ D.AD C.II C.IH C.SR C.SS C.QQ D.FA D.06 C.HH D.86 C.HQ D.A6 C.RR D.B8 C.TT C.QH D.D6 D.5D D.2E C.HH D.83 C.JK C.RS D.C7 D.69 D.32 C.HH D.8E C.HQ D.A7 D.59 C.TS C.TR C.SR C.QQ D.F5 C.RR D.BB D.57 D.2D C.HI D.90 C.TT C.TR C.SR C.SR C.QQ D.FF D.7F D.3F acter that is received is placed into the Receive FIFO (when enabled) or into the Receive Output Register ...
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... The Receive Output Register changes in response to the ris- ing edge of RXCLK. The Receive FIFO status flag outputs of this register are placed in a High-Z state when the CY7C9689 is not addressed (CE is sampled HIGH). The RXDATA bus output drivers are enabled when the device is selected by ...
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... RXD[6] RXD[7] RXD[8] RXD[9] VLTN Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Operating Range Range Commercial +0.5V DD Industrial +0. CY7C9689 [1] Encoded 10-bit Pre-encoded 12-bit [9] Character Stream Character Stream RXSC/D [10, 12] RXDATA[0] RXD[0] RXDATA[1] RXD[1] RXDATA[2] RXD[2] RXDATA[3] RXD[3] ...
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... CY7C9689 DC Electrical Characteristics Parameter Description TTL Outputs V Output HIGH Voltage OHT V Output LOW Voltage OLT I Output Short Circuit Current OST I High-Z Output Leakage Current OZL TTL Inputs V Input HIGH Voltage IHT V Input LOW Voltage ILT I Input HIGH Current IHT I Input LOW Current ...
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... TTLAC Test Load 3.0V 3.0V 2.0V V =1.5V th 0.8V 0.0V < (c) TTL Input Test Waveform CY7C9689 Transmitter TTL Switching Characteristics, FIFO Enabled Parameter f TXCLK Clock Cycle Frequency With Transmit FIFO Enabled TS t TXCLK Period TXCLK t TXCLK HIGH Time TXCPWH t TXCLK LOW Time ...
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... CY7C9689 Receiver TTL Switching Characteristics, FIFO Enabled Parameter f RXCLK Clock Cycle Frequency With Receive FIFO Enabled RIS t RXCLK Input Period RXCLKIP t RXCLK Input HIGH Time RXCPWH t RXCLK Input LOW Time RXCPWL [16] t RXCLK Input Rise Time RXCLKIR [16] t RXCLK Input Fall Time ...
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... CY7C9689 Receiver TTL Switching Characteristics, FIFO Bypassed Parameter [20] f RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation ROS (SPDSEL is HIGH and BYTE8/10 is HIGH) RXCLK Clock Output Frequency—50 to 100 MBaud 8-bit Operation (SPDSEL is LOW and BYTE8/10 is HIGH) RXCLK Clock Output Frequency—100 to 200 MBaud 10-bit Operation (SPDSEL is HIGH and BYTE8/10 is LOW) RXCLK Clock Output Frequency— ...
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... CY7C9689 Receiver Switching Characteristics Parameter [23] t Bit Time B [16, 24] t Static Alignment SA [16, 25, 26] t Error Free Window EFW t IN± Peak-to-Peak Input Jitter Tolerance IN_J CY7C9689 Transmitter Switching Characteristics Parameter [23] t Bit Time B t PECL Output Rise Time 20 80% (PECL Test Load) ...
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... CY7C9689 HOTLink Transmitter Switching Waveforms Write Cycle Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH t TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY Write Cycle Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY Notes: 31 ...
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... CY7C9689 HOTLink Transmitter Switching Waveforms OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXRST TXFULL TXHALF TXEMPTY OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] XDATA[9:8]/TXCMD[2:3] ...
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... CY7C9689 HOTLink Transmitter Switching Waveforms Write Cycle Synchronous Interface EXTFIFO=HIGH t REFH FIFOBYP=LOW REFCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY Write Cycle Synchronous Interface EXTFIFO=LOW FIFOBYP=LOW REFCLK TXHALT TXSC/D TXDATA[7:0] DATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY Notes: 34 ...
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... CY7C9689 HOTLink Transmitter Switching Waveforms OUTPUT ENABLE Timing Synchronous Interface EXTFIFO=HIGH FIFOBYP=LOW REFCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN CE TXFULL TXEMPTY OUTPUT ENABLE Timing Synchronous Interface EXTFIFO=LOW FIFOBYP=LOW REFCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN CE TXFULL TXEMPTY (continued ...
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... CY7C9689 HOTLink Receiver Switching Waveforms Read Cycle Asynchronous (FIFO) Interface EXTFIFO=HIGH FIFOBYP=HIGH RXCLK t RXENS RXEN READ Note 36 RXEMPTY LFI RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] CE Read Cycle Asynchronous (FIFO) Interface EXTFIFO=LOW FIFOBYP=HIGH RXCLK t RXENS t READ RXEN RXEMPTY LFI RXFULL RXHALF RXDATA[7:0] ...
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... CY7C9689 HOTLink Receiver Switching Waveforms Output Enable Timing RXCLK RXEN RXRST LFI RXFULL RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] t REFCLK Static Alignment INA INB SAMPLE WINDOW Notes: 39. Illustrates timing only. RXEN and RXRST not usually active in same time period. ...
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... CY7C9689 5B/6B Encoder 5-bit Binary 6-bit Encoded [41] [42, 43] Data Symbol 00000 110110 00001 010001 00010 100100 00011 100101 00100 010010 00101 010011 00110 010110 00111 010111 01000 100010 01001 ...
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... Table 8. HOTLink TAXI Compatible Command Symbols CY7C9689 (Transmitter) Command Input TXCMD[3:0] [44] HEX Binary CMD 8-bit mode (BYTE8/10 is HIGH) 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 [45] 8 1000 [45] 9 1001 [45] A 1010 B 1011 C 1100 [45] D 1101 [45] E 1110 [45] F 1111 10-bit mode (BYTE8/10 is LOW) ...
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... SEL and RANGESEL inputs) to generate the serial data bit- clock. In this mode, part of the TXCMD bus inputs are used as part of the data input bus. To place the CY7C9689 into syn- chronous modes, FIFOBYP must be LOW. This mode is usually used for products containing external en- coders or scramblers, that must meet specific protocol require- ments ...
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... Asynchronous Decoded In Asynchronous Decoded mode, both the Receive FIFO and the Decoder of the CY7C9689 are enabled. The deserializer operates synchronous to the recovered bit-clock, which is di- vided generate the Receive FIFO write clock. Charac- ters are read from the Receive FIFO, using the external RXCLK input, when addressed by CE and selected by RXEN ...
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... BIST are documented in Table 4. BIST Enable Inputs There are separate BIST enable inputs for the transmit and receive paths of the CY7C9689. These inputs are both active LOW; i.e., BIST is enabled in its respective section of the de- vice when the BIST enable input is determined logic- 0 level. Both BIST enable inputs are asynchronous ...
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... FIFO status flags remain in a high-Z state and the loop event is lost. This is also true of the VLTN output, such that if the CY7C9689 receive path is not selected to enable the RXDATA bus three-state driv- ers, the detection of a BIST miscompare is lost. ...
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... FIFOs at any rate up to the maximum 50-MHz clock rate of the FIFOs. All internal operations of the CY7C9689 do not use the external TXCLK or RXCLK, but in- stead make use of synthesized derivatives of REFCLK for transmit path operations and a recovered character clock for receive path operations ...
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... Synchronous With Shared Bus Timing and Control (Transmit FIFO Bypassed) When the Transmit FIFO is bypassed (FIFOBYP is LOW and not in byte-packed mode), the CY7C9689 must still be select write data into the Transmit Input Register. When CE is sampled LOW and TXRST is sampled HIGH by the rising edge of REFCLK, a Tx_Match condition is generat- ed ...
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... Bus Timing) TXDATA/TXCMD (Cascade Timing) TXFULL Figure 9. Transmit Selection with Transmit FIFO Bypassed Notes: 46.Signals labeled in italics are internal to the CY7C9689. 47.Signals shown as dotted lines represent the differences in timing and active state of signals when operated in Cascade Timing. Note ...
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... Synchronous With UTOPIA Timing and Control (Receive FIFO Bypassed) When the Receive FIFO is bypassed (FIFOBYP is LOW), the CY7C9689 must still be selected to enable the output drivers for the RXDATA bus. With the Receive FIFO bypassed, RXCLK becomes a synchronous output clock operating at the charac- ter rate ...
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... Figure 15 shows a sequence of input signals which will not produce a FIFO reset. In this case TXEN was asserted to se- lect a Transmit FIFO for data transfers. Because TXEN re- mains active, the assertion of CE and TXRST does not initiate 43 CY7C9689 ...
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... Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH). 49. Signal names listed in italics are internal signals, shown for reference only. Note 48 Note ration of the seven-state reset counter. Note 48 Note Figure 13. Transmit FIFO Reset Sequence 44 CY7C9689 ...
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... FULL and later going EMPTY when the internal reset is complete, there is no secondary in- dication of the completion of the internal reset of the Receive FIFO. The Receive FIFO is usable as soon as new data is placed into it by the Receive Control State Machine. 45 CY7C9689 ...
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... Note [49 stM [49 atch [49 Note Figure 16. Receive FIFO Reset Sequence 46 CY7C9689 ...
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... CY7C9689. OUTA± OUTB± INA± INB± Power Supply Bypass 0.01- F MLC X7R CY7C9689-AC CY7C9689-AC Power Supply Bypass 0.01- F MLC X7R Other layouts, including cases with components mounted on the reverse side would work as well. 47 CY7C9689 CURSETB ...
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... Ordering Information Ordering Code Package Name CY7C9689-AC A100 CY7C9689-AI A100 Document #: 38-00758-*C Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 HOTLink is a registered trademark of Cypress Semiconductor, Inc. AMD, TAXI, and TAXIchip are trademarks of Advanced Micro Devices. Inc. ©Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...