CY7C1368B-166AC Cypress Semiconductor Corporation., CY7C1368B-166AC Datasheet
CY7C1368B-166AC
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CY7C1368B-166AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05419 Rev. ** Functional Description The CY7C1368B SRAM integrates 262,144 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all ...
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... Document #: 38-05419 Rev A[1:0] Q1 BURST COUNTER AND LOGIC CLR BYTE WRITE DRIVER DQ C MEMORY BYTE ARRAY WRITE DRIVER DQ B BYTE WRITE DRIVER DQ A BYTE WRITE DRIVER PIPELINED ENABLE CY7C1368B OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS E INPUT REGISTERS Page [+] Feedback ...
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... Document #: 38-05419 Rev. ** 100-pin TQFP Top View CY7C1368B 65 (256K x 32 CY7C1368B DDQ V SSQ SSQ V DDQ ...
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... Document #: 38-05419 Rev. ** 100-pin TQFP Top View CY7C1368B 65 (256K x 32 CY7C1368B DDQ V SSQ SSQ V DDQ ...
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... CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition. CY7C1368B [ and CE 1 ...
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... A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1368B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1368B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... BWE Test Conditions ZZ > > < 0.2V This parameter is sampled This parameter is sampled CY7C1368B ADV WRITE OE CLK L L-H three-state ...
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... V = Max., Device Deselected, All speeds /2), undershoot: V (AC)> -2V(Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1368B Ambient ) DDQ 3.3V 5%/+10% 3. Min. Max. 3.135 3.6 3.135 V DD 2.4 0.4 2 0.3V DD – ...
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... R = 351 INCLUDING JIG AND SCOPE (b) [15, 16] Description Min. [11] 5.0 2.0 2.0 1.25 1.25 1.25 and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1368B TQFP Package Unit 25 °C/W 9 °C/W Max. Unit ALL INPUT PULSES DD 90% 90% 10% ...
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... WEH [ Data Input Hold After CLK Rise DH t Chip Enable Hold After CLK Rise CEH Document #: 38-05419 Rev. ** [15, 16] Description Min. [12, 13, 14] [12, 13, 14] 1.5 1.5 1.5 Hold After CLK Rise 0.5 CY7C1368B 200 MHz 166 MHz Max. Min. Max. Unit 3.0 3.5 ns 1.5 ns 1.5 1.5 ns 1.5 1 ...
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... CO t OELZ t OEHZ t DOH Q(A2 Q(A1) BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1368B A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Q(A3) Burst wraps around to its initial state is HIGH LOW HIGH. ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05419 Rev. ** ADSC extends burst A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. [A:D] CY7C1368B t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in Tri-State following a WRITE cycle unless a new read access is initiated by ADSP or ADSC . 20 HIGH . Document #: 38-05419 Rev WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE BURST READ UNDEFINED DON’T CARE CY7C1368B A5 A6 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Ordering Information [23] Speed (MHz) Ordering Code 166 CY7C1368B-166AC 166 CY7C1368B-166AJC Notes: 21. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 22. DQs are in tri-state when exiting ZZ sleep mode. 23. Please contact your local Cypress sales representative for availability of 200-MHz speed grade option. ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1368B 51-85050-*A ...
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... Document History Page Document Title: CY7C1368B 9M (256K x 32) Pipelined DCD Sync SRAM Document Number: 38-05419 REV. ECN NO. Issue Date ** 130317 12/30/03 Document #: 38-05419 Rev. ** Orig. of Change Description of Change AJU New Data Sheet CY7C1368B Page [+] Feedback ...