CY7C1353-40AC Cypress Semiconductor Corporation., CY7C1353-40AC Datasheet
CY7C1353-40AC
Related parts for CY7C1353-40AC
CY7C1353-40AC Summary of contents
Page 1
... The CY7C1353 is a 3.3V 256K by 18 Synchronous- Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL ) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle ...
Page 2
... DDQ DDQ 100-Pin TQFP CY7C1353 2 CY7C1353 DDQ DDQ ...
Page 3
... When left floating MODE will default HIGH inter- leaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the device. Should be connected to ground of the system. 3 CY7C1353 controls DQ and DP , BWS 0 [7:0] 0 ...
Page 4
... Read/Modify/Write sequences, which can be reduced to sim- ple byte write operations. Because the CY7C1353 is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQ three-state the output drivers ...
Page 5
... X L Valid L signifies at least one Byte Write Select is active, BWS x 5 CY7C1353 Comments I/Os three-state following next rec- ognized clock. Clock Ignored, all operations sus- pended. Address Latched. Address Latched, data presented two valid clocks later. Burst Read Operation. Previous access was a Read operation. Ad- dresses incremented internally in conjunction with the state of Mode ...
Page 6
... Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 +150 C Operating Range +125 C 0.5V to 4.6V Range Com’l 0. 0.5V DDQ 0. 0.5V DDQ 6 CY7C1353 Second Third Fourth Address Address Address Ax+1, Ax Ax+1, Ax Ax+ ...
Page 7
... Device Deselected, All speed grades 0.3V DDQ Max Device Deselected, or 15-ns cycle, 66 MHz > DDQ 20-ns cycle, 50 MHz 1/t MAX CYC 25-ns cycle, 40 MHz 7 CY7C1353 Min. Max. Unit 3.135 3.465 V 3.135 3.465 V 2.4 V 0.4 V 2 0.3 0 ...
Page 8
... AC Test Loads. Test Conditions MHz 3. 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND 1353-2 SCOPE (b) Test Conditions Symbol 8 CY7C1353 Max. Unit [11] ALL INPUT PULSES 3.0V 1353-3 TQFP Typ. Units Notes ...
Page 9
... High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. [11, 12, 13] –66 Min. Max. 15.0 5.0 5.0 2.0 0.5 1.5 2.0 0.5 2.0 0.5 2.0 0.5 1.7 0.5 2.0 0.5 5.0 2.0 [10,12,13,14] 6.0 [10,12,13,14] 0 6.0 is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ 9 CY7C1353 –50 –40 Min. Max. Min. Max. 20.0 25.0 6.0 7.0 6.0 7.0 2.0 2.5 1.0 1.0 11 12.0 14.0 1.5 1.5 2.0 2.5 1.0 1.0 2.0 2.5 1.0 1.0 2.0 2.5 1.0 1.0 2.0 2.5 1.0 1 ...
Page 10
... CL CH CYC WA5 RA4 RA6 t DOH t CHZ Out In Out to define a Write Cycle (see Write Cycle Description Table and CE . All Chip Selects need to be active in order to select 3 = UNDEFINED = DON’T CARE 10 CY7C1353 t t CENH CENS RA7 t CHZ Q6 Q7 Out Out ...
Page 11
... AH AS WA2 CHZ DH Q1+2 Q1+3 D2 D2+1 Out Out defines a write cycle (see Write Cycle Description Table). , and CE . All Chip Enables need to be active in order to select UNDEFINED = DON’T CARE 11 CY7C1353 RA3 t CLZ Q3 D2+2 D2+3 Q3+1 Out In In Out input signals. [1:0] ...
Page 12
... Switching Waveforms OE Timing Ordering Information Speed (MHz) Ordering Code 66 CY7C1353-66AC 50 CY7C1353-50AC 40 CY7C1353-40AC Document #: 38-00689 EOHZ Three-state I/O’s t EOLZ Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack ...
Page 13
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1353 51-85050-A ...