CY28341ZC Cypress Semiconductor Corporation., CY28341ZC Datasheet
CY28341ZC
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CY28341ZC Summary of contents
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Universal Single-Chip Clock Solution for VIA P4M266/KM266 Features • Supports VIA P4M266/KM266 chipsets • Supports Pentium® 4, Athlon™ processors • Supports two DDR DIMMS • Supports three SDRAMS DIMMS at 100 MHz • Provides: — Two different programmable CPU clock ...
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Pin Description Pin Name PWR 3 XIN 4 XOUT VDD 1 FS0/REF0 VDD 56 VTTPWRGD# VDDR REF1 VDDR 44,42,38, DDRT VDDD 36,32,30 (0:5)/SDRAM(0,2,4,6, 8,10) 43,41,37 DDRC VDDD 35,31,29 (0:5)/SDRAM(1,3,5,7, 9,11) 7 SELP4_K7 / AGP1 VDDAG 12 MULTSEL / PCI2 ...
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Pin Description (continued) Pin Name PWR 11 SELSDR_DDR#/PCI VDDPCI 1 21 FS2/24_48M VDD48M I/O 6 AGP0 VDDAG 8 AGP2 VDDAG 25 IREF 28 SDATA 27 SCLK 26 PD#/SRESET# 45 BUF_IN 46 FBOUT 5 VDDAGP 51 VDDC 16 VDDPCI 55 ...
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Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. ...
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Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits “1xxxxxxx” stands for byte operationbit[6:0] of the ...
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Byte 2: PCI Clock Register Bit @Pup Pin# Name 7 0 PCI_DRV PCI_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 ...
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Byte 5: SDR/DDR Clock Register Bit @Pup Pin# Name BUF_IN threshold voltage FBOUT 5 1 29,30 DDRT/C5/SD RAM(10,11 31,32 DDRT/C4/SD RAM(8, 35,36 DDRT/C3/SD RAM(6, 37,38 DDRT/C2/SD RAM(4,5) 1 ...
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Byte 7: Dial-a-Frequency Control Register N Bit @Pup Pin Reserved 6 0 N6, MSB N0, LSB Byte 8: Silicon Signature Register ...
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Table 9. Spread Spectrum Table Mode SST1 SST0 Swing Select Functions Through Hardware MULT- Board Target ...
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Maximum Ratings Input Voltage Relative to V :.............................. V SS Input Voltage Relative DDQ Storage Temperature: ................................– 150 C Operating Temperature: .................................... +70 C Maximum ESD .............................................................2000V Maximum Power ...
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AC Parameters (continued) Parameter Description Vcross Crossing Point Voltage at 0.7V Swing P4 Mode CPU at 1.0V TDC CPUT/C Duty Cycle TPeriod CPUT/C Period Differential CPUT/C Rise and Fall Times Tr/Tf TSKEW CPUCS_T/C to CPUT/C Clock Skew TCCJ CPUT/C Cycle ...
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AC Parameters (continued) Parameter Description 48MHz Rise and Fall Times TCCJ 48MHz Cycle to Cycle Jitter 24MHz TDC 24MHz Duty Cycle TPeriod 24MHz Period 24MHz Rise and Fall Times TCCJ 24MHz Cycle to Cycle ...
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P4 Processor SELP4_K7 Power-down Assertion (P4 Mode) When PD# is sampled LOW by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held LOW on their next HIGH to LOW transition. ...
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Rise and Fall Times Power-down Deassertion (P4 Mode) The power-up latency needs to be less than 3 mS ...
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133M 133M 133M ...
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Power-down Deassertion (K7 Mode) When de-asserted PD# to HIGH level, all clocks are enabled and start running on the rising edge of the next full period ...
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Figure 7. Clock Generator Power-up/ Run State Diagram (with P4 Processor SELP4_K7 Connection Circuit DDRT/C Signals For Open ...
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Table 10. Signal Loading Table REF (0:1), 48MHz (USB), 24_48MHz AGP(0:2), SDRAM (0:11) PCI_F(0:5) DDRT/C (0:5), FBOUT CPUT/C CPUOD_T/C CPUCS_T/C For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1) The following diagram shows lumped test load configurations for the ...
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... CY28341OC 56-pin Shrunk Small Outline package (SSOP) CY28341OCT 56-pin Shrunk Small Outline package (SSOP)–Tape and Reel CY28341ZC 56-pin Thin Shrunk Small Outline package (TSSOP) CY28341ZCT 56-pin Thin Shrunk Small Outline package (TSSOP)–Tape and Reel Document #: 38-07367 Rev. *A 10ns 20ns t ...
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Package Drawing and Dimensions 56-lead Thin Shrunk Small Outline Package, Type × 12 mm) Z56 Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights ...
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Document Title: CY28341 Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems Document Number: 38-07367 Issue REV. ECN NO. Date ** 112783 05/28/02 *A 122908 12/26/02 Document #: 38-07367 Rev. *A Orig. of Change Description of Change DMG New Data ...