MC14569BCL Motorola, MC14569BCL Datasheet
MC14569BCL
Available stocks
Related parts for MC14569BCL
MC14569BCL Summary of contents
Page 1
... Plastic “P and D/DW” Packages: – 7.0 mW From 125 _ C Ceramic “L” Packages: – From 100 125 _ C CTL = Low for Binary Count CTL = High for BCD Count 9 CLOCK CASCADE 7 FEEDBACK REV 3 1/94 MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 Value Unit – 0 18.0 V – 500 ...
Page 2
... Adc 5.0 7.5 — — pF 0.005 5.0 — 150 Adc 0.010 10 — 300 0.015 20 — 600 Adc ( out ) MOTOROLA CMOS LOGIC DATA ...
Page 3
... Clock Pulse Frequency Clock Pulse Rise and Fall Time #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance CLOCK CLOCK ZERO DETECT MOTOROLA CMOS LOGIC DATA ( pF Vdc Vdc Symbol Symbol t TLH 5.0 ...
Page 4
... MC14522B or the MC14526B, the Cascade Feedback input, Q, and Zero Detect outputs must be respectively connected to “0”, Clock, and Load of the following counter. If the MC14569B is used alone, Cascade Feedback must be con- nected DETECT CASCADE 5.0 V FEEDBACK + 100 PIN ASSIGNMENT ZERO CTL1 CTL CLOCK MOTOROLA CMOS LOGIC DATA ...
Page 5
... Counter #2 Binary Output (Always Low) MOTOROLA CMOS LOGIC DATA Divide Ratio CTL 2 Zero Detect 0 256 1 160 0 160 1 100 (CTL 1 = Low, CTL 2 = Low, Cascade Feedback = High) Divide Ratio Zero Detect 256 256 127 128 128 ...
Page 6
... Output (Always Low) MC14569B 6 (CTL 1 = High, CTL 2 = Low, Cascade Feedback = High) Divide Ratio Zero Detect 160 160 150 150 159 159 Counter #1 BCD Comments Comments Max Count Illegal State Min Count Q Output Active Bit Value Counting Sequence MOTOROLA CMOS LOGIC DATA ...
Page 7
... Table 4. Mode Controls Preset Values 128 Counter #2 BCD Output (Always Low) MOTOROLA CMOS LOGIC DATA (CTL 1 = Low, CTL 2 = High, Cascade Feedback = High) Divide Ratio Zero Detect 160 160 112 128 128 144 144 159 159 Counter #1 Binary Comments Comments Max Count ...
Page 8
... OUTPUT BY 4 DIVIDE BY 12 MC14569B 8 (CTL 1 = High, CTL 2 = High, Cascade Feedback = High) Divide Ratio Zero Detect 100 100 Counter #1 BCD TIMING DIAGRAM MC14569B Comments Comments Max Count illegal state Min Count Q Output Active Bit Value Counting Sequence MOTOROLA CMOS LOGIC DATA ...
Page 9
... CTL CASCADE FEEDBACK 9 CLOCK CTL 2 MOTOROLA CMOS LOGIC DATA LOGIC DIAGRAM ZERO DETECT 15 MC14569B 9 ...
Page 10
... DP0 – – – – – – DP3 VCO MC14011 CF C (Channel Spacing 10 kHz) Q4 Q1/C2 MC14568B “0” PE “0” DP0 – – – – – – DP3 f out MSD f out (144 – 146 MHz MIXER CRYSTAL OSCILLATOR (143.5 MHz) MOTOROLA CMOS LOGIC DATA ...
Page 11
... N SEATING PLANE 0.25 (0.010 –A– 0.25 (0.010) M MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –B– 0.25 (0.010 SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R L SEATING –T– PLANE ...
Page 12
... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...