LC72720Y Sanyo Semiconductor Corporation, LC72720Y Datasheet
LC72720Y
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LC72720Y Summary of contents
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... Ordering number : ENN6488 Overview The LC72720Y and LC72720YV are single-chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator, ...
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... X OUT 12 Top view Block Diagram V REF +3.3V Vdda REFERENCE VOLTAGE Vssa 57kHz MPXIN ANTIALIASING (SCF) FILTER DO CL CCB (24 BLOCK DATA MEMORY CONTROL T2 TEST LC72720Y, 72720YV unit: mm 3191A-SSOP30 13 12 SANYO: DIP24S 24 SYR V REF 23 CE MPXIN 22 DI Vdda Vssa 19 RDS-ID FLOUT 18 SYNC CIN ...
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... Digital system ground Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications. Pins 4, 8, 12, 19, 23, 27 are NC (NO CONNECT) Pins for the SSOP package version. LC72720Y, 72720YV Function Serial data interface (CCB) I/O ...
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... Data latch change time Data output time Electrical Characteristics –40 to +85°C, Vssd = Vssa = 0 V Parameter Input resistance Internal feedback resistance Center frequency –3 dB bandwidth Gain Stop band attenuation LC72720Y, 72720YV Symbol Conditions V max Vddd, Vdda max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC ...
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... OWD RF1 RF0 ARI SYC D15 D14 D13 D12 D11 D10 (1) Offset word detection flag (1 bit): OWD OWD Offset word detection 1 Detected 0 Not detected (protection function operating) LC72720Y, 72720YV Symbol Conditions G-Delay FLOUT ± 1.2 kHz Vref VREF : Vdda = 3 CL, DI, CE, SYR, T1, T2 ...
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... When the error flags EC0 to EC2 are 011 (indicating that correction is not possible) the data must be handled as invalid data. (8) RDS data (16 bits D15 This data is output with the MSB first and the LSB last. Caution: When error correction was not possible, the input data is output without change. LC72720Y, 72720YV ...
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... BS Synchronization detection conditions 0 If during 3 blocks, 2 blocks of offset words were detected in the correct order the offset words were detected in the correct order in 2 consecutive blocks. Initial value LC72720Y, 72720YV IN1 data, first bit * * * OWEEC0 EC1 EC2 EC3 EC4 CT0 IN2 data, first bit ...
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... When ARI is present, PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner. LC72720Y, 72720YV Normal write (See the description of the OWE bit.) After the reset is cleared, start writing from the data prior to the establishment of synchronization, i ...
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... Number of error blocks ( ≤ B ≤ < B ≤ < B ≤ 48 These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values listed in the table. LC72720Y, 72720YV Decoding method T5 T6 RSFT ERROR 57K — ...
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... RDDA output RSFT output Timing 2 (mode 3, PT2 = 0) Sync NG Input data Error crrection SYNC output ERROR output CORREC output LC72720Y, 72720YV The SYNC pin The RDS-ID pin High (1) Low (0) Notes These states are user settable Users cannot use this state Control When set to 1, soft-decision control data (RSFT) is easier to generate. ...
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... B1 Internal data CL: Normal low Internal data LC72720Y, 72720YV (MSB · Control data input mode, also referred to as “serial data input” mode · This is a 16-bit data input mode. · Control data input mode, also referred to as “serial data input” mode. ...
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... DO and CE pins separately if the number of available microcontroller ports allows it.) 3. Serial data I/O becomes possible after the crystal oscillator starts oscillation. Serial data timing CL: Normal high Intenal data latch CL: Normal low Intenal data latch LC72720Y, 72720YV ≥ 0.75 µ < 0.46 µ ...
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... One method is to read out data from the LC72720Y and either check whether meaningful data has been read (if the LC72720Y is not requesting a read, data consisting of all zeros will be read out) or check whether the DO level goes low within the 265 µs following the completion of the read (if the DO pin goes low, then the request was from another IC) ...
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... Sample Application Circuit (LC72720Y) Vssa MPXIN 330pF Vdda 560pF Notes: 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed 100-kΩ bias resistor must be connected between the CIN pin and the VREF pin the SYR pin is unused, it must be connected to ground. ...