TC5565APL TOSHIBA Semiconductor CORPORATION, TC5565APL Datasheet
TC5565APL
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TC5565APL Summary of contents
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... TOSHIBA MOS MEMORY PRODUCTS DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns. ...
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... T Operating Temperature opr * -3.0V at pulse width 50ns MAX. **Flat package D.C RECOMMENDED OPERATING CONDITIONS SYMBOL V Power Supply Voltage DD V Input High Voltage IH V Input Low Voltage IL V Data-Retention Supply Voltage DH TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 CE2 \ ITEM PARAMETER R/W ...
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... CE2 >= V – 0.2V or CE2 <= 0.2V. DD CAPACITANCE (Ta=25 °C ) SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT * This parameter periodically sampled is not 100% tested. TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 °C TEST CONDITION V O~V IN= DD VOH-2-4V VOL-0. CE2-VOL or IH \CE1 = V or CE2 ...
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... R/W to Output High-Z ODW r R/W to Output Low-Z OEW t Data Set up Time DS t Data Hold Time DH A.C. TEST CONDITION Output Load Input Pulse Level Timing Measurement V Reference Level TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ° 5V±10%) DD TC5565APL-10 TC5565AFL-10 MIN. 100 - - - - TC5565APL-10 TC5565AFL-10 MIN. ...
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... TIMING WAVEFORMS READ CYCLE (1) WRITE CYCLE 1 (4) (R/W Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ...
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... WRITE CYCLE 2 (4) (\CE1 Controlled Write) WRITE CYCLE 3 (4) (CE2 Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ...
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... Stand by Supply Current I DDS2 t Chip Deselection to Data Retention Mode CDR t Recovery Mode R Note (1) : Read cycle Time. \CE1 Controlled Data Retention Mode (2) CE2 Controlled Data Retention Mode (4) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Ta=0~70 °C) PARAMETER VDD=3.0V VDD=5.5V MIN. TYP. MAX. UNIT 2 ...
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... In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V. DEVICE INFORMATION The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous. Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient. ...
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... No.1 and No.28 leads. MFP 28 PIN OUTLINE DRAWING (F28GC-P) Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each lead that is obtained on the basis of No.1 and N0.28 leads TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Unit in mm Unit in mm ...