TDA7572TR STMicroelectronics, TDA7572TR Datasheet - Page 42

• Manufacturer Part Number: TDA7572TR
• Description: IC AMP PWM 200W BRIDGE 64HIQUAD
• Manufacturer: STMicroelectronics
• Type: Class Dr

Specifications of TDA7572TR

• Output Type: 1-Channel (Mono)
• Voltage - Supply: 8 V ~ 58 V
• Features: Digital Inputs, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Standby
• Mounting Type: Surface Mount
• Package / Case: 64-HiQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Max Output Power X Channels @ Load: -

Modulator
7.1
42/64
Table 32.
Pulse injection is being used with the clocked PWM scheme to prevent missing pulses from
an over-modulation condition. The minimum pulse width is dynamically determined by
looking at the delay from the comparator output to the actual switching of the FET stage.
This delay is used to extend any pulses from the modulator that would otherwise be too
short. Circuitry is provided to keep the integrator hovering near the level at which limiting
first occurred, which prevents transients once we leave the over modulation condition. This
is done by summing in a current that is proportional to the amount of time that the pulse is
extended.
Since only three- state modulation is supported, it may prove necessary to slightly delay the
clock going to one modulator to prevent the noise from the switching of one modulator
affecting the second modulator when there is no audio input. This can be done with a small
RC on the clock feeding one modulator. The same result could be obtained adding the RC
on the feedback feeding one modulator.
The reference voltage of the modulator changes from SVR at it's input, to Vcc/2 at its output.
This allows output signal to be centered between the supply rails, increasing unclipped
output voltage swing by preventing asymmetric clipping. This is accomplished using the
LVLSFT pin, as described in the previous paragraph. It has been pointed out that there is
potential for abrupt transients at the output stage, as this scheme will attempt to have the
outputs track VCC/2, while it may be better for avoiding pops to have them rise slowly with
SVR. The end user needs to make this decision by making or not the connection between
HVCC and LVLSFT pin. Will not be present pop noise in a system with perfect symmetry
between the two modulators branch. Pop noise will rise with increasing of asymmetry.
FET drive
Gate drive circuits are provided to drive complementary external FETS. An internal regulator
to supply the low side gate drivers provides a voltage 10V above VSM. This fully enhances
the FETs without exceeding their V
for the high side gate drivers.
Shoot-through is prevented by sensing V
(GateSensing), and blocking the opposite FET turn-on if the active FET in a ½ bridge has a
|V
without concern over shoot-through.
The drivers are capable to provide high current for a short time (about 5µs) and a lower
current after this time(~150mA). This is done to give enough charge current at the
commutation and avoid short-cut overcurrent.
The V
overcurrent condition. The sensed V
when the FET is enhanced and any turn on transients have settled. There are two type of
overcurrent intervention: current limitation, cycle-by-cycle limitation. The current limitation
GS
|> |V
DS
PWMClock [1:0]
of the enhanced FET of each ½ bridge is used monitor current and detect
Threshold
PWMClock table
00
01
10
11
|. This allows discrete components to be used to adjust gate charging
GS
DS
F
F
Ratio
F
F
NOM
limits. A separate regulator 10V below V
NOM
NOM
NOM
signal is blanked such that sensing is only active
GS
*2
/2
of each FET with a dedicated sense line
Nominal frequency
110KHz
220KHz
110KHz
55KHz
SP
, is used
TDA7572