ADRF6602ACPZ-R7 Analog Devices Inc, ADRF6602ACPZ-R7 Datasheet - Page 2

• Manufacturer Part Number: ADRF6602ACPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADRF6602ACPZ-R7

• Lead Free Status / Rohs Status: Compliant

ADRF6602
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Register Structure ........................................................................... 16
REVISION HISTORY
9/10—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 and Table 4 ....................................................... 4
Changes to Table 6 ............................................................................ 6
Changes to Typical Performance Characteristics Section ........... 9
Added Spurious Performance Section ......................................... 15
Changes to Programming the ADRF6602 Section .................... 20
Added AC Test Fixture Section and Figure 47 ........................... 23
Changes to Evaluation Board Control Software Section ........... 24
7/10—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
Changes to Table 6 ............................................................................ 6
Changes to Figure 20 ...................................................................... 14
Changes to Figure 21 ...................................................................... 17
Changes to Figure 22 ...................................................................... 18
Changes to Figure 23 ...................................................................... 19
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications ................................................... 4
Logic Input and Power Specifications ....................................... 4
Timing Characteristics ................................................................ 5
ESD Caution .................................................................................. 6
RF Frequency Sweep .................................................................... 9
IF Frequency Sweep ................................................................... 10
Spurious Performance................................................................ 15
Register 0—Integer Divide Control (Default: 0x0001C0)..... 16
Register 1—Modulus Divide Control (Default: 0x003001) .. 16
Register 2—Fractional Divide Control (Default: 0x001802) 17
Rev. C | Page 2 of 32
Theory of Operation ...................................................................... 20
Applications Information .............................................................. 22
AC Test Fixture ............................................................................... 23
Evaluation Board ............................................................................ 24
Outline Dimensions ....................................................................... 29
4/10—Rev. 0 to Rev. A
Added Table 1 .................................................................................... 1
Changes to Figure 1 ........................................................................... 1
Change to Synthesizer/PLL Specifications Section ....................... 4
Change to Table 3 .............................................................................. 4
Changes to Initializing Sequence Section ................................... 15
Changes to Figure 16 ...................................................................... 12
Changes to Figure 17 ...................................................................... 13
Changes to Figure 19 ...................................................................... 14
Changes to Figure 21 ...................................................................... 17
Changes to Figure 24 ...................................................................... 20
1/10—Revision 0: Initial Version
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B) .................................................................................... 17
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4) ................................................... 18
Register 5—PLL Enable and LO Path Control (Default:
0x0000E5) .................................................................................... 19
Register 6—VCO Control and VCO Enable (Default:
0x1E2106) .................................................................................... 19
Register 7—Mixer Bias Enable and External VCO Enable
(Default: 0x000007) .................................................................... 19
Programming the ADRF6602 ................................................... 20
Initialization Sequence .............................................................. 20
LO Selection Logic ..................................................................... 21
Basic Connections for Operation ............................................. 22
Evaluation Board Control Software ......................................... 24
Schematic and Artwork ............................................................. 26
Evaluation Board Configuration Options ............................... 28
Ordering Guide .......................................................................... 29