PC16550DV/NOPB National Semiconductor, PC16550DV/NOPB Datasheet - Page 19

• Manufacturer Part Number: PC16550DV/NOPB
• Description: IC UART WITH FIFO 44-PLCC
• Manufacturer: National Semiconductor

Specifications of PC16550DV/NOPB

• Features: Modem Control Function
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 4.5 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• No. Of Channels: 1
• Data Rate: 1.5Mbps
• Uart Features: Independently Controlled Transmit, Receive, Line Status, And Data Set Interrupts
• Supply Voltage Range: 4.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *PC16550DV; *PC16550DV/NOPB; PC16550DV

8 0 Registers
Bit 7 This bit is the complement of the Data Carrier Detect
(DCD) input If bit 4 of the MCR is set to a 1 this bit is
equivalent to OUT 2 in the MCR
8 10 SCRATCHPAD REGISTER
This 8-bit Read Write Register does not control the UART
in anyway It is intended as a scratchpad register to be used
by the programmer to hold data temporarily
8 11 FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are enabled
(FCR0
A The receive data available interrupt will be issued to the
B The IIR receive data available indication also occurs
C The receiver line status interrupt (IIR
D The data ready bit (LSR0) is set as soon as a character is
When RCVR FIFO and receiver interrupts are enabled
RCVR FIFO timeout interrupts will occur as follows
A A FIFO timeout interrupt will occur if the following condi-
B Character times are calculated by using the RCLK input
C When a timeout interrupt has occurred it is cleared and
D When a timeout interrupt has not occurred the timeout
When the XMIT FIFO and transmitter interrupts are enabled
(FCR0
A The transmitter holding register interrupt (02) occurs
CPU when the FIFO has reached its programmed trigger
level it will be cleared as soon as the FIFO drops below
its programmed trigger level
when the FIFO trigger level is reached and like the inter-
rupt it is cleared when the FIFO drops below the trigger
level
tions exist
The maximum time between a received character and a
timeout interrupt will be 160 ms at 300 baud with a 12-bit
receive character (i e 1 Start 8 Data 1 Parity and 2 Stop
Bits)
for a clock signal (this makes the delay proportional to
the baudrate)
when the XMIT FIFO is empty it is cleared as soon as
the transmitter holding register is written to (1 to 16 char-
acters may be written to the XMIT FIFO while servicing
this interrupt) or the IIR is read
has higher priority than the received data available
(IIR
transferred from the shift register to the RCVR FIFO It is
reset when the FIFO is empty
the timer reset when the CPU reads one character from
the RCVR FIFO
timer is reset after a new character is received or after
the CPU reads the RCVR FIFO
e
e
e
04) interrupt
1 IER0
1 IER1
at least one character is in the FIFO
the most recent serial character received was
longer than 4 continuous character times ago (if 2
stop bits are programmed the second one is in-
cluded in this time delay)
the most recent CPU read of the FIFO was longer
than 4 continuous character times ago
e
e
1) RCVR interrupts will occur as follows
1) XMIT interrupts will occur as follows
(Continued)
e
06) as before
19
B The transmitter FIFO empty indications will be delayed 1
Character timeout and RCVR FIFO trigger level interrupts
have the same priority as the current received data avail-
able interrupt XMIT FIFO empty has the same priority as
the current transmitter holding register empty interrupt
8 12 FIFO POLLED MODE OPERATION
With FCR0
zero puts the UART in the FIFO Polled Mode of operation
Since the RCVR and XMITTER are controlled separately
either one or both can be in the polled mode of operation
In this mode the user’s program will check RCVR and XMIT-
TER status via the LSR As stated previously
There is no trigger level reached or timeout condition indi-
cated in the FIFO Polled Mode however the RCVR and
XMIT FIFOs are still fully capable of holding characters
9 0 Typical Applications
character time minus the last stop bit time whenever the
following occurs THRE
least two bytes at the same time in the transmit FIFO
since the last THRE
ter changing FCR0 will be immediate if it is enabled
LSR0 will be set as long as there is one byte in the RCVR
FIFO
LSR1 to LSR4 will specify which error(s) has occurred
Character error status is handled the same way as when
in the interrupt mode the IIR is not affected since
IER2
LSR5 will indicate when the XMIT FIFO is empty
LSR6 will indicate that both the XMIT FIFO and shift reg-
ister are empty
LSR7 will indicate whether there are any errors in the
RCVR FIFO
e
0
e
1 resetting IER0 IER1 IER2 IER3 or all to
High-Capacity Data Bus
Typical Interface for a
e
1 The first transmitter interrupt af-
e
1 and there have not been at
TL C 8652 – 23