SCC2698BC1A84,512 NXP Semiconductors, SCC2698BC1A84,512 Datasheet - Page 15

• Manufacturer Part Number: SCC2698BC1A84,512
• Description: IC UART OCTAL ENHANCED 84-PLCC
• Manufacturer: NXP Semiconductors
• Type: Octal UARTr

Specifications of SCC2698BC1A84,512

• Number Of Channels: 8
• Package / Case: 84-LCC (J-Lead)
• Features: False-start Bit Detection
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 115.2 Kbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1120-5; 933976250512; SCC2698BC1A84

Philips Semiconductors
MR2[5] – Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows:
1. Program the auto-reset mode: MR2[5]=1
2. Enable transmitter, if not already enabled
3. Assert RTSN via command
4. Send message
5. Disable the transmitter after the last byte of the message is
6. The last character will be transmitted and the RTSN will be reset
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2[4] – Clear-to-Send Control
The sate of this bit determines if the CTSN input (MPI) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (Low), the
character is transmitted. If it is negated (High), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes Low. Changes in CTSN, while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a mark condition at the center of
the first stop bit position (one bit time after the last data bit, or after
the parity bit if parity is enabled). If an external 1X clock is used for
the transmitter, MR2[3] = 0 selects one stop bit and MR2[3] = 1
selects two stop bits to be transmitted.
2006 Aug 07
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
loaded to the TxFIFO. At the time the disable command is
issued, be sure that the transmitter ready bit is on and the
transmitter empty bit is off. If the transmitter empty bit is on
(indicating the transmitter is underrun) when the disable is
issued, the last byte will not be sent.
one bit time after the last stop bit is sent.
15
CSR – Clock Select Register
Table 3. Baud Rate
The receiver clock is always a 16X clock, except for CSR[7:4] =
1111. When MPP2 is selected as the input, MPP2a is for channel a
and MPP2b is for channel b. See Table 5.
CSR[7:4] – Receiver Clock Select
When using a 3.6864MHz crystal or external clock input, this field
selects the baud rate clock for the receiver as shown in Table 3.
CSR[3:0] – Transmitter Clock Select
This field selects the baud rate clock for the transmitter. The field
definition is as shown in Table 3, except as follows:
CSR[3:0]
1 1 1 0
1 1 1 1
When MPP1 is selected as the input, MPP1a is for channel a and
MPP1b is for channel b.
CR – Command Register
CR is used to write commands to the Octal UART.
CR[7:4] – Miscellaneous Commands
The encoded value of this field can be used to specify a single
command as follows:
NOTE: Access to the upper four bits of the command register
should be separated by three (3) edges of the X1 clock.
0000
0001
0010
0011
0100
CSR[7:4]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
No command.
Reset MR pointer. Causes the MR pointer to point to
MR1.
Reset receiver. Resets the receiver as if a hardware
reset had been applied. The receiver is disabled and the
FIFO pointer is reset to the first location.
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
Reset error status. Clears the received break, parity
error, framing error, and overrun error bits in the status
register (SR[7:4]}. Used in character mode to clear OE
status (although RB, PE, and FE bits will also be
cleared), and in block mode to clear all error status after
a block of data has been received.
ACR[7] = 0
MPP1 – 16X
MPP1 – 1X
ACR[7] = 0
MP2 – 16X
MP2 – 1X
Timer
134.5
1,200
1,050
2,400
4,800
7,200
9,600
38.4k
110
200
300
600
50
ACR[7] = 1
MPP1 – 16X
MPP1 – 1X
SCC2698B
Product data sheet
ACR[7] = 1
MP2 – 16X
MP2 – 1X
38.4k
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
110
150
300
600
75