SC16IS760IPW,112 NXP Semiconductors, SC16IS760IPW,112 Datasheet - Page 31

• Manufacturer Part Number: SC16IS760IPW,112
• Description: IC UART 64BYTE 24TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS760IPW,112

• Number Of Channels: 1, UART
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4185; 935279287112; SC16IS760IPW; SC16IS760IPW

NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
8.10 Enhanced Features Register (EFR)
8.11 Division registers (DLL, DLH)
This 8-bit register enables or disables the enhanced features of the UART.
the enhanced feature register bit settings.
Table 22.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced Features Register bits description
Description
CTS flow control enable
RTS flow control enable.
Special character detect
Enhanced functions enable bit
Combinations of software flow control can be selected by programming these
bits. See
Single UART with I
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO resume transmission trigger level TCR[7:4] is reached.
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to FIFO
and IIR[4] is set to a logical 1 to indicate a special character has been
detected.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
so that they can be modified.
Rev. 06 — 13 May 2008
Table 3 “Software flow control options
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
(EFR[3:0])”.
© NXP B.V. 2008. All rights reserved.
Table 22
shows
31 of 62