PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 126

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

3.7.5.3
If the TE frame structure on the IOM-2 interface is selected, the same D-channel access
procedures as described in
For other frame structures used in LT-T mode, D-channel access on S is handled
similarly, with the difference that the S/G bit is not available on IOM-2 but only on the
S/G bit output pin (SGO).
3.7.5.4
In intelligent NT applications (selected via register TR_MODE.MODE2-0) the ISAC-SX
has to share the upstream D-channel with one or more D-channel controllers on the
IOM-2 interface and with all connected TEs on the S interface.
The transceiver incorporates an elaborate statemachine for D-channel priority handling
on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S
interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on
IOM-2. Due to this an equal and fair access is guaranteed for all D-channel sources on
both the S interface and the IOM-2 interface.
This arbitration mechanism is only available in IOM-2 TE mode (12 PCM timeslots) per
frame with enabled TIC bus. The access to the upstream D-channel is handled via the
S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are
inverted to block the terminals on S). Furthermore, if more than one HDLC source is
requesting D-channel access on IOM-2 the TIC bus mechanism is used.
The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the
necessary number of “1s” is counted and an HDLC controller on IOM-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or
10 (TR_CMD.DPRIO).
The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/
G bit is not evaluated in this mode.
The configuration settings of the ISAC-SX in intelligent NT applications are summarized
in
Data Sheet
Table
14.
S-Bus D-Channel Control in LT-T
D-Channel Control in the Intelligent NT (TIC- and S-Bus)
Chapter 3.7.5.2
126
are used in LT-T mode.
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX