DS2151Q/T&R Maxim Integrated Products, DS2151Q/T&R Datasheet
DS2151Q/T&R
Specifications of DS2151Q/T&R
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DS2151Q/T&R Summary of contents
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FEATURES ƒ Complete DS1/ISDN-PRI Transceiver Functionality ƒ Line Interface Can Handle Both Long- and Short-Haul Trunks ƒ 32-Bit or 128-Bit Jitter Attenuator ƒ Generates DSX-1 and CSU Line Build-Outs ƒ Frames to D4, ESF, and SLC-96 ƒ Dual On-Board ...
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DETAILED DESCRIPTION....................................................................................................4 1.1 I ................................................................................................................................ 4 NTRODUCTION 2 PIN DESCRIPTION................................................................................................................6 2.1 DS2151Q R M EGISTER 3 PARALLEL PORT .................................................................................................................9 4 CONTROL REGISTERS......................................................................................................10 4 ......................................................................................................................... 15 OCAL OOPBACK 4 ...................................................................................................................... 15 EMOTE OOPBACK 4 ...
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Figure 1-1. DS2151Q Block Diagram ......................................................................................................... 5 Figure 13-1. External Analog Connections............................................................................................... 43 Figure 13-2. Jitter Tolerance .................................................................................................................... 43 Figure 13-3. Transmit Waveform Template .............................................................................................. 44 Figure 13-4. Jitter Attenuation .................................................................................................................. 45 Figure 14-1. Receive Side D4 Timing....................................................................................................... 46 Figure ...
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DETAILED DESCRIPTION The DS2151Q T1 single-chip transceiver (SCT) contains all the necessary functions for connection to T1 lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 ...
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Figure 1-1. DS2151Q Block Diagram DS2151Q ...
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PIN DESCRIPTION PIN NAME TYPE 1–4, AD4–AD7, I/O 41–44 AD0–AD3 RD(DS ALE(AS WR(R/ RLINK O 10 RLCLK O 11 DVSS — 12 RCLK O 13 RCHCLK O 14 RSER ...
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PIN NAME TYPE 20 BTS I RTIP, 21, 22 — RRING 23 RVDD — 24 RVSS — XTAL1, 25, 26 — XTAL2 INT1 27 O INT2 TTIP — 30 TVSS — 31 TVDD — 32 TRING — ...
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DS2151Q Register Map ADDRESS R/W REGISTER NAME 20 R/W Status Register 1 21 R/W Status Register 2 22 R/W Receive Information Register 1 Line Code Violation Count 23 R Register 1 Line Code Violation Count 24 R Register 2 ...
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PARALLEL PORT The DS2151Q is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2151Q can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing ...
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CONTROL REGISTERS The operation of the DS2151Q is configured via a set of eight registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2151Q has been initialized, the control registers will ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address = 2C Hex) (MSB) RCS RZBTSI SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSDW RSM RSIO NAME AND DESCRIPTION Receive Code Select. 0 ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 35 Hex) (MSB) LOTCMC TFPT SYMBOL POSITION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 RBSE TCR1.4 GB7S TCR1.3 TLINK TCR1.2 TBL TCR1.1 TYEL TCR1.0 Note: For a detailed description of how the bits in ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex) (MSB) TEST1 TEST0 TZBTSI SYMBOL POSITION TEST1 TCR2.7 TEST0 TCR2.6 TZBTSI TCR2.5 TSDW TCR2.4 TSM TCR2.3 TSIO TCR2.2 TD4YM TCR2.1 B7ZS XTCR2.0 Table 4-1. Output Pin Test Modes TEST1 TEST0 0 ...
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CCR1: COMMON CONTROL REGISTER 1 (Address = 37 Hex) (MSB) TESE LLB SYMBOL POSITION TESE CCR1.7 LLB CCR1.6 RSAO CCR1.5 RLB CCR1.4 SCLKM CCR1.3 RESE CCR1.2 PLB CCR1.1 FLB CCR1.0 RSAO RLB SCLKM NAME AND DESCRIPTION Transmit Elastic Store Enable. ...
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Local Loopback When CCR1.6 is set the DS2151Q will be forced into Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received ...
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CCR2: COMMON CONTROL REGISTER 2 (Address = 38 Hex) (MSB) TFM TB8ZS TSLC96 SYMBOL POSITION TFM CCR2.7 TB8ZS CCR2.6 TSLC96 CCR2.5 TFDL CCR2.4 RFM CCR2.3 RB8ZS CCR2.2 RSLC96 CCR2.1 RFDL CCR2.0 TFDL RFM RB8ZS NAME AND DESCRIPTION Transmit Frame Mode ...
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CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex) (MSB) ESMDM ESR SYMBOL POSITION ESMDM CCR3.7 ESR CCR3.6 P16F CCR3.5 RSMS CCR3.4 PDE CCR3.3 TLD CCR3.2 TLU CCR3.1 LIRST CCR3.0 P16F RSMS PDE NAME AND DESCRIPTION Elastic Store Minimum Delay ...
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Loop Code Generation When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted payload with either the Loop Up or Loop Down code, respectively. The DS2151Q will overwrite the repeating loop ...
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STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real time status of the DS2151Q: Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register 1 (RIR1), and Receive Information ...
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address = 22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 16ZD RESF RESE NAME AND DESCRIPTION Change of Frame Alignment. ...
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex) (MSB) RL1 RL0 SYMBOL POSITION RL1 RIR2.7 RL0 RIR2.6 TESF RIR2.5 TESE RIR2.4 TSLIP RIR2.3 JALT RIR2.2 RPDV RIR2.1 TPDV RIR2.0 Table 5-1. Receive T1 Level Indication TYPICAL LEVEL RL1 RL0 ...
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SR1: STATUS REGISTER 1 (Address = 20 Hex) (MSB) LUP LDN SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 RCL SR1.1 RLOS SR1.0 LOTC RSLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. Set ...
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Table 5-2. Alarm Set and Clear Criteria ALARM Blue Alarm (AIS) (see note below) Yellow Alarm 1. D4 bit 2 mode (RCR2.2= F-bit mode (RCR2.2=1; this mode is also referred to as the “Japanese Yellow Alarm”) ...
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SR2: STATUS REGISTER 2 (Address = 21 Hex) (MSB) RMF TMF SYMBOL POSITION RMF SR2.7 TMF SR2.6 SEC SR2.5 RFDL SR2.4 TFDL SR2.3 RMTCH SR2.2 RAF SR2.1 — SR2.0 SEC RFDL TFDL NAME AND DESCRIPTION Receive Multiframe. Set on receive ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address = 7F Hex) (MSB) LUP LDN SYMBOL POSITION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 RCL IMR1.1 RLOS IMR1.0 LOTC SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 6F Hex) (MSB) RMF TMF SYMBOL POSITION RMF TMF SEC RFDL TFDL RMTCH RAF — SEC RFDL TFDL NAME AND DESCRIPTION IMR2.7 Receive Multiframe interrupt masked 1 = interrupt enabled IMR2.6 ...
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ERROR COUNT REGISTERS There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive synchronization. ...
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Path Code Violation Count Register (PCVCR) When the receive side of the DS2151Q is set to operate in the ESF framing mode (CCR2.3 = 1), PCVCR will automatically be set as a 12-bit counter that will record errors in ...
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Multiframes Out of Sync Count Register (MOSCR) Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0 = 1). This number is useful in ESF applications needing to measure ...
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FDL/FS EXTRACTION AND INSERTION The DS2151Q can extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit position, this capability ...
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RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex) RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex) (MSB) RFDL7 RFDL6 SYMBOL POSITION RFDL7 RFDL0 When the byte in the Receive FDL Register matches either of the two ...
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SIGNALING OPERATION The Robbed-Bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2151Q. There is a set of 12 registers for the receive side (RS1 ...
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address = Hex) (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) ...
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TRANSMIT TRANSPARENCY AND IDLE REGISTERS There is a set of seven registers in the DS2151Q that can be used to custom tailor the data that transmitted onto the T1 line channel-by-channel basis. Each of ...
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 3F Hex) (MSB) TIDR7 TIDR6 TIDR5 SYMBOL POSITION TIDR7 TIDR0 Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in the outgoing frame. When these bits are ...
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CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...
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ELASTIC STORES OPERATION The DS2151Q has two on-board two-frame (386 bits) elastic stores. These elastic stores have two main purposes. First, they can be used to rate-convert the T1 data stream to 2.048Mbps (or a multiple of 2.048Mbps), which ...
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RECEIVE MARK REGISTERS The DS2151Q can replace the incoming data on a channel-by-channel basis with either an idle code (7F hex) or the digital milliwatt code, which is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). ...
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LINE INTERFACE FUNCTIONS The line interface function in the DS2151Q contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of these three sections ...
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Receive Clock and Data Recovery The DS2151Q contains a digital clock recovery system. See The DS2151Q couples to the receive T1 twisted pair via a 1:1 transformer. See transformer details. The DS2151Q automatically adjusts to the T1 signal being ...
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Transmit Waveshaping and Line Driving The DS2151Q uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the DS2151Q meet ...
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Jitter Attenuator The DS2151Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in ...
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Figure 13-1. External Analog Connections NOTE: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE. Figure 13-2. Jitter Tolerance DS2151Q ...
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Figure 13-3. Transmit Waveform Template DS2151Q ...
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Figure 13-4. Jitter Attenuation DS2151Q ...
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TIMING DIAGRAMS Figure 14-1. Receive Side D4 Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RCR2 AND ...
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Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. NOTE 2: AN ESF BOUNDARY IS SHOWN. Figure 14-4. 1.544MHz Boundary Timing with Elastic Store(s) Enabled NOTE 1: RSYNC IS IN ...
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Figure 14-5. 2.048MHz Boundary Timing with Elastic Store(s) Enabled NOTE 1: RSER DATA IN CHANNELS 13, 17, 21, 25, AND 29 ARE FORCED TO 1; TSER IGNORED DURING THESE CHANNELS. NOTE 2: RSYNC IS IN THE OUTPUT ...
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Figure 14-7. Transmit Side ESF Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0). NOTE 2: TSYNC IN THE FRAME MODE (TCR2 AND DOUBLE-WIDE FRAME SYNC ...
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Figure 14-8. Transmit Side Boundary Timing with Elastic Store(s) Disabled NOTE 1: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0). NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL ...
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Figure 14-9. Transmit Data Flow DS2151Q ...
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DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V Operating Temperature Range Commercial…………………………………………………………...………..……...0qC to +70qC Industrial…………………………………………………………………………….-40qC to +85qC Storage Temperature ………………………………………………………………………-55qC to +125qC Soldering Temperature...………………………………………..See IPC/JEDEC J-STD-020 Specification This is a stress rating ...
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AC CHARACTERISTICS Table 16-1. AC Characteristics—Parallel Port = 5V r5 0qC to +70qC for DS2151Q (See Figure 16-1, Figure 16-2, and PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, ...
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Figure 16-1. Intel Bus Read AC Timing Figure 16-2. Intel Bus Write AC Timing DS2151Q ...
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Figure 16-3. Motorola Bus AC Timing DS2151Q ...
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Table 16-2. AC Characteristics—Receive Side = 5V r5 0qC to +70qC for DS2151Q (See Figure 16-4.) PARAMETER ACLKI/RCLK Period RCLK Pulse Width RCLK Pulse Width SYSCLK Period SYSCLK Pulse Width RSYNC Setup to SYSCLK ...
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Figure 16-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1). NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. ...
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Table 16-3. AC Characteristics—Transmit Side = 5V r5 0qC to +70qC for DS2151Q (See Figure 16-5.) PARAMETER TCLK Period TCLK Pulse Width TSER and TLINK Set up to TCLK Falling TSER and TLINK Hold ...
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Figure 16-5. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0). NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF SYSCLK IF ...
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