NS32FX200VF-25 National Semiconductor, NS32FX200VF-25 Datasheet

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... Supports two stepper motors Y Direct interface to ROM and SRAM The NS32FX200 Y and NS32FV100 in addition interface to DRAM devices FIGURE 1-1 A FAX Controller Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRE TM and WATCHDOG TM are trademarks of National Semiconductor Corporation C 1995 National Semiconductor Corporation ...

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FAX SYSTEM CONFIGURATION 1 1 Block Diagram Description 1 2 Module Diagram Bus and Memory Controller (BMC Timing Control Unit (TCU Sigma-Delta CODEC (SDC Scanner Controller ...

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Table of Contents 2 0 ARCHITECTURE (Continued Bus and Memory Controller (BMC Features Operation Zones 0 1 (ROM and SRAM) Transactions Zone 2 (Dynamic ...

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FIGURE 1-1 A FAX Controller Block Diagram FIGURE 1-2 NS32FX100 Module Diagram FIGURE 1-3 NS32FV100 Module Diagram FIGURE 1-4 NS32FX200 Module Diagram FIGURE 1-5 System Chip States and Operation Modes FIGURE 2-1 Clocks and Traps Connectivity FIGURE 2-2 High Speed ...

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FIGURE 4-1 Connection Diagram Top View FIGURE 4-2 Analog Circuitry Block Diagram FIGURE 4-3 TTL Output Signals Specification Standard FIGURE 4-4 TTL Input Signals Specification Standard FIGURE 4-5 CMOS Output Signals Specification Standard FIGURE 4-6 CMOS Input Signals Specification Standard ...

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Fax-System Configuration A typical FAX system based on the NS32FX100 NS32FX200 or NS32FV100 is shown in Figure 1 BLOCK DIAGRAM DESCRIPTION CPU The typical FAX system shown below is based on a single embedded processor The ...

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Fax-System Configuration 1 2 MODULE DIAGRAM The various functions of the NS32FX100 NS32FV100 and NS32FX200 are performed by on-chip modules as shown below The NS32FX100 module diagram is shown in Figure 1-2 FIGURE 1-2 NS32FX100 Module Diagram The ...

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Fax-System Configuration The NS32FX100 modules and their functions are summa- rized below For a more detailed description of each mod- ule see the relevant section Bus and Memory Controller (BMC) The Bus and Memory Controller ...

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Fax-System Configuration power-fail input is asynchronous It is recognized by the NS32FX100 during cycles in which the input setup-time re- quirement is satisfied Switching from Normal mode to Power Save mode and vice versa must always be carried ...

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Architecture 2 1 MCFG MODULE CONFIGURATION REGISTER The software can configure some of the NS32FX100 major operation modes by programming the Module Configuration Register (MCFG) Some of the bits in this register are also used to initialize the ...

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Architecture (Continued External Clocks The TCU contains two oscillators the high-speed oscillator and the low-speed oscillator The high-speed oscillator is the FAX system clocking source It generates the CPU clock and after division clocks ...

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Architecture (Continued Registers CSCL CCLK (CPU Input Clock) Scale register res F F Controls the CCLK frequency 1 The CCLK frequency is the FOSCI input frequency divided The ...

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... NSFAX Software package fully supports the SDC Software drivers handle both the SDC initialization and data transfers National Semiconductor’s modem software is usually pro- vided in binary form and hence the internal structure of the SDC is transparent to the user A detailed description of the ...

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Architecture (Continued) FIGURE 2-4 Sigma-Delta Block Diagram 11331 – 9 ...

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Architecture (Continued) A full Sigma-Delta CODEC includes a digital part and an analog part The NS32FX100 includes the digital part and the analog part should be implemented externally On-Chip Digital Blocks Sigma-Delta Over Sampling ...

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Architecture (Continued) 16 ...

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Architecture (Continued Analog Transmitter The input to the transmit analog circuit is the serial bit stream at OSR which is generated by DSDM This serial bit stream is fed to a 1-bit D A ...

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Architecture (Continued) SDTGC Transmit Gain Control register Used to attenuate the transmit IIR input samples The value to be written in SDTGC register is 16384 rounded to the nearest integer number Some examples are given in the following ...

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Architecture (Continued Scanner Signals Generator Block This block generates the timing control signals required by CIS and CCD scanners Scanners with line scan time ...

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Architecture (Continued Scanner Period Pulse (SPP) Generation The Scanner Period Pulse (SPP) is used to synchronize all the scanner control signals It is derived from the time slots generated by the TCU module (which ...

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Architecture (Continued) SLS Pulse Generation Scan Line Sync (SLS) is generated by a timer according to a calculated delay (in CTTL cycles) from the beginning of the SPP pulse The delay between the beginning of SPP and the ...

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Architecture (Continued) Video DAC (Shading-Compensation) The shading-compensation circuit includes an 8-bit multiply- ing Digital-to-Analog Converter (DAC) that multiplies SVI the analog input from an external video sample and hold circuit with a digital reference value (white line) fetched ...

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Architecture (Continued) Pixel Generator Pixels may be treated in one of three ways No bypass The output of the video comparator is an image pixel It may be inverted by the pixel generator before the pixel is shifted ...

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Architecture (Continued res LSPP PDWP DISP Scanner Discharge Pulse Polarity 0 Active low 1 Active high SNHP Sample and Hold Pulse Polarity 0 Active low 1 Active high PDWP Peak Detector Window Polarity 0 ...

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Architecture (Continued) 8 The peak detector window may be used to disable the ABC circuit outside the programmed window The ac- tive video window and the peak detector window are configured separately thus allowing a peak detector window ...

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Architecture (Continued) Strobes Generator A train of strobes consists of two or four strobes depending on the strobes mode The train of strobe pulses starts on the time slot pre-defined in the Printer Strobes-Start Time Slot (PSTSL) register ...

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Architecture (Continued) Printer Interrupt Generator The Interrupt Control Unit dedicates one interrupt either to the Strobes-Done pulse or to DMA channel 1 The Printer Interrupt Source (PIS) bit of the TPHC register selects which of the interrupt pulses ...

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Architecture (Continued Registers PBCFG Printer Bitmap Shifter Configuration register 7 2 res ECLK External Clock (NS32FX200 only ) 0 Shift using an internal clock Clock frequency is selected by the printer bitmap internal clock generator ...

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Architecture (Continued) b Initialize the PRNTC module to work with an external clock c Initialize DMA channel 1 registers without enabling the channel (set CNTL1 CHEN Set MCFG ECOUNT and MCFG EPBMS to ‘‘1’’ to ...

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Architecture (Continued) Memory-to-I O Operation The data is first read from the source into the DMA Control- ler and is subsequently written to the destination When the DIR bit is ‘‘0’’ the first bus-cycle is used to read ...

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Architecture (Continued) DEC Decrement Increment update of ADCA 0 ADCA incremented after each transfer cycle (if ADA ADCA decremented after each transfer cycle (if ADA 1) e NFBY Fly-By Memory-to-I O Transfers for channel 3 ...

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Architecture (Continued) (3) The OVR bit in the STAT register is set to ‘‘1’’ and the EOVR bit is ‘‘1’’ In the last case the CHEN bit is forced to ‘‘0’’ and cannot be set to ‘‘1’’ by ...

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Architecture (Continued) FIGURE 2-16 DMA Fly-By Write Transaction (DIR The maximum throughput of a DMA channel Mbyte sec (Two bytes can be transferred at a rate of four CTTL cycles per transfer ...

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Architecture (Continued) FIGURE 2-17 DMA Memory (Indirect) Read Transaction (DIR The maximum throughput of a DMA channel is 3 125 Mbyte sec (One byte can be transferred at a rate of eight CTTL cycles per ...

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Architecture (Continued) FIGURE 2-18 DMA Memory Write Transaction (DIR The maximum throughput of a DMA channel is 3 125 Mbyte sec (One byte can be transferred at a rate of eight CTTL cycles per transfer ...

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Architecture (Continued) FIGURE 2-19 Two Adjacent Fly-By DMA Transactions The maximum throughput of a DMA channel Mbyte sec (Two bytes can be transferred at a rate of four CTTL cycles per transfer ...

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Architecture (Continued) A transmit interrupt is generated on transmit ready if not masked by the UMASK register A receive interrupt is gener- ated if not masked by the UMASK register on receive ready for every received character regardless ...

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Architecture (Continued TBRK res res res TSB EDB EPS Even Parity Select 0 Odd parity 1 Even parity Even parity means that the total number of bits set (including the parity bit) ...

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Architecture (Continued) Accessing MWSIO while the MWIRE is busy (MWCSR BUSY 1) may cause unpredictable e results MWCSR MICROWIRE Control and Status register res CLKM CDV BUSY Read only Set to ‘‘1’’ during MWIRE ...

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Architecture (Continued Usage Recommendations 1 Before activating the MICROWIRE program the appro- priate Ports module registers PBDO PBMS PCDO PCMS and PCEN to connect the MICROWIRE module to the NS32FX100 I O pins 2 The ...

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Architecture (Continued Registers IVCT Interrupt Vector register Read only 8-bit regis- ter INTVECT INTVECT When INTR pin is active this field contains the encoded value of ...

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Architecture (Continued) with other modules and are allocated by software Input pins can always be read even if shared with another mod- ule Output pins can be enabled or disabled (TRI-STATE) The characteristics of the four bits which ...

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Architecture (Continued) Four bits are associated with each general purpose I O pin of this port DI Data In Bit DO Data Out Bit EN Enable Bit MS Module Select Bit Port input data is asynchronous When the ...

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Architecture (Continued) PCDI Port C data in Read only Holds the current value of the pins (latched once each CTTL SBPYS PCLK SNH UREN UTXD MWSO DMRQ2 DMRQ1 DMRQ0 PCDO Port C ...

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Architecture (Continued) PCEN Port C Enable EN7 EN6 EN5 EN4 EN3 EN2 EN0–EN7 Enable bit for Port C output pins A pin is driven when its relevant ENi bit is set to ...

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Architecture (Continued) Memory transactions are either adjacent (back-to-back) or spaced with idle cycles To increase pre-charge time and to avoid contention on the AD0–AD15 bus the memory trans- actions may be spaced by idle cycles When an IDLEi ...

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Architecture (Continued other memory transactions address bits A12–A15 are driven onto MA12–MA15 in T1 (non-multiplexed) CAS is asserted low in T3 Once CAS is asserted the transaction may be extended by wait states denoted by T3W ...

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Architecture (Continued) IDLE1 Zone 1 SRAM idle control See IDLEi below WAIT2 Zone 2 DRAM wait state control See WAITi below IDLE2 Zone 2 DRAM idle control See IDLEi below WAITi Number of T3W (wait) extension cycles (i ...

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Architecture (Continued) l ETC rw FE0500 31 ETC l RFEN rw FE0505 NS32FX200 and only res EN res l RFRT rw FE0506 NS32FX200 and only 7 RFRT SDC l SDCNTL rw FE01E0 ...

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Architecture (Continued) l SCMPRW w FE0220 7 SCMPRW l SPRES w FE0222 7 SPRES l SVHC rw FE0240 res BYPASS INVERT VDILS l SVDB rw FE0242 15 SVDB l SBMS r FE0244 15 SBMS ...

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Architecture (Continued) l CNTL0 FFF03E l CNTL1 FFF05E l CNTL2 FFF07E l CNTL3 FFF09E NS32FX200 only 7 2 res UART l UCNTL rw FE0601 TBRK res res res TSB EDB l UMASK ...

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Architecture (Continued) PORTS l PBDO rw FE0812 SDIS SCLK2 DMAK3 DMAK1 STB3 STB2 DMAK2 DMAK0 res SLS SCLK1 l PBMS rw FE0814 ...

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System Interface 3 1 POWER AND GROUNDING The NS32FX100 requires a 5V 10% supply to nine digital g pins and supply to two analog pins Two pins g provide analog ground nine pins provide digital ...

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System Interface (Continued BUS CYCLES Memory transactions issued by the CPU and the NS32FX100 are almost identical The transactions differ as follows 1 During the CPU transactions data is driven onto AD0–15 throughout T4 whereas on ...

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System Interface (Continued) FIGURE 3-5 Zones 0 1 (ROM SRAM) Write Transaction Zero Wait State FIGURE 3-6 Zones 0 1 (ROM SRAM) Write Transaction One Wait State 11331 – 11331– 38 ...

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System Interface (Continued) FIGURE 3-7 Zone 2 (DRAM) Refresh Transaction Zero Wait State If a new CPU DMA transaction to either Zone started during the refresh transaction it is postponed by CWAIT until ...

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System Interface (Continued) FIGURE 3-10 Zone 2 (DRAM) Read Transaction Zero Wait State ( ) Note OE or WEi according to other Zone 0 or Zone 1 access figures FIGURE 3-11 Zones 0 1 Access Delayed by a ...

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System Interface (Continued) FIGURE 3-12 Zone 2 (DRAM) Read Transaction One Wait State FIGURE 3-13 Zone 2 (DRAM) Write Transaction Zero Wait State 11331 – 11331– 45 ...

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System Interface (Continued) FIGURE 3-14 Zone 2 (DRAM) Write Transaction One Wait State FIGURE 3-15 Zone Read Transaction Two Wait States 11331– 11331– 47 ...

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System Interface (Continued) FIGURE 3-16 Zone Read Transaction Four Wait States FIGURE 3-17 Zone Write Transaction Four Wait States 11331 – 11331 – 49 ...

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System Interface (Continued) FIGURE 3-18 Zone Write Transaction Six Wait States FIGURE 3-20 Spaced Memory Transaction Two Tidles after T4 FIGURE 3-19 CPU DMA Arbitration 11331– 11331 – 51 ...

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Device Specifications 4 1 NS32FX100 PIN DESCRIPTIONS The following is a brief description of all NS32FX100 pins Some NS32FX100 pins have flexible allocation These pins can be individually configured as general purpose pins even Supplies ...

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Device Specifications Output Signals Signal Pin Numbers BUZCLK 59 Buzzer Clock Programmable frequency clock for the buzzer CAS 104 DRAM Column Address Strobe Column address strobe for DRAM banks refresh (NS32FX200 and NS32FV100 ) CCLK ...

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Device Specifications Output Signals (Continued) Signal Pin Numbers SDIS DMAK2 27 SDOUT 20 SEL0 108 SEL1 110 SEL3 107 SLS 21 SMPH0 – SOSCO 63 SPDW 23 STB0 – ...

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Device Specifications (Continued OUTPUT SIGNAL LEVELS The following tables show the levels of the NS32FX100 output control signals during reset or power save mode Freeze Mode Output Signals Output signals are driven during ...

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Device Specifications (Continued) 132-Pin PQFP Package Top View FIGURE 4-1 Connection Diagram 11331 – 54 ...

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... Device Specifications (Continued ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature under Bias Storage Temperature ELECTRICAL CHARACTERISTICS 10% GND CCD g Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage ...

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Device Specifications (Continued ELECTRICAL CHARACTERISTICS 10% GND CCD Symbol Parameter I Leakage Current Output L and I O Pins in TRI-STATE or Input ...

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Device Specifications (Continued ANALOG ELECTRICAL CHARACTERISTICS CCA g GND Video MDAC Resolution Monotonicity Nonlinearity REF I Range OFF ...

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Device Specifications (Continued SWITCHING CHARACTERISTICS Definitions All the timing specifications given in this section refer the rising or falling edges of all the signals as illustrated ...

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Device Specifications Timing Tables Output Signals Internal Propagation Delays Symbol Figure Description t 4-8 CCLK Clock Period CLKp t 4-8 CCLK High Time CLKh t 4-8 CCLK Low Time CLKl t ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays (Continued) Reference Symbol Figure Description t 4-16 A16–23 Valid After R E AHv CTTL T1 t 4-16 A16–23 Hold After R ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays (Continued) Symbol Figure Description t 4-15 RAS0–1 Signal Active RASBBa (Freeze Mode) t 4-15 RAS0–1 Signal Active RASBBia (Freeze Mode) t ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays (Continued) Symbol Figure Description t 4-23 SMPH0–3 Signal SMPHa Active t 4-23 SMPH0–3 Signal SMPHia Inactive t 4-21 STB0–3 Signal STBa ...

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Device Specifications Timing Tables (Continued Output Signals Internal Propagation Delays (Continued) Symbol Figure Description t 4-24 UTXD Signal UTXDa Active t 4-24 UTXD Signal UTXDia Inactive t 4-24 UREN Signal URENa ...

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Device Specifications Timing Tables (Continued Input Signal Requirements Symbol Figure Description t 4-8 CTTL Clock R E CTTL to CTp Period Next R E CTTL t 4-8 CTTL High At 2 ...

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Device Specifications Timing Tables (Continued Input Signal Requirements (Continued) Reference Symbol Figure Description Condition t 4-9 ADS Signal Before R E ADSs Setup CTTL T2 t 4-9 ADS Pulse At 0 ...

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Device Specifications Timing Tables (Continued Input Signal Requirements (Continued) Reference Symbol Figure Description Condition t 4-24 URXD Signal Before R E URXDs Setup CTTL t 4-24 URXD Signal After R E ...

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Device Specifications (Continued) FIGURE 4-8 Clock Waveforms FIGURE 4-9 DRAM Read Bus Cycle 11331 – 11331– 62 ...

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Device Specifications (Continued) FIGURE 4-10 DRAM Write Bus Cycle 11331 – 63 ...

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Device Specifications (Continued) FIGURE 4-11 ROM SRAM Read Bus Cycle 11331– 64 ...

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Device Specifications (Continued) FIGURE 4-12 ROM SRAM Write Bus Cycle (One Wait State 11331 – 65 ...

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Device Specifications (Continued) FIGURE 4- Read Bus Cycle FIGURE 4- Write Bus Cycle 11331– 11331– 67 ...

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Device Specifications (Continued) FIGURE 4-15 DRAM Refresh Bus Cycles 11331 – 11331 – 69 ...

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Device Specifications (Continued) FIGURE 4-16 DMA Read Transaction (DIR Note t and t are irrelevant in Fly-By mode when the implied external i e when the DMA channel is used as an external channel Ds ...

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Device Specifications (Continued) Note CPU drives ADS A16–23 DDIN when HLDA becomes inactive FIGURE 4-17 DMA Write Transaction (DIR Note t t and t irrelevant in Fly-By mode when the implied external i e when ...

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Device Specifications (Continued) FIGURE 4-18 Interrupt Signals Timing FIGURE 4-19 Sigma-Delta Signals Timing FIGURE 4-20 SBYPS Input Signal Timing TL EE 11331 – 11331– 11331– 73 ...

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Device Specifications (Continued) FIGURE 4-21 Printer Signals Timing FIGURE 4-22 Reset Signals Timing 11331 – 11331 – 76 ...

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Device Specifications (Continued) Note For convenience all the above signals are shown on the same diagram The diagram shows the relationship between each signal and CTTL only There is no significance in the relationships between individual signals See ...

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Device Specifications (Continued) FIGURE 4-24 UART Signals Timing FIGURE 4-25 Mwire Signals Timing 11331– 11331 – 79 ...

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Device Specifications (Continued) FIGURE 4-26 Ports Signals Timing FIGURE 4-27 Analog Signals Timing 11331– 11331– 81 ...

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Appendix A Codec Transmission Performance The Sigma Delta Codec transmission performance of a typi- cal complete system including DAA is according to the fol- lowing test conditions The measurement analog circuit is according to Figure 2-5 The measurements are performed ...

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Appendix A Codec Transmission Performance TABLE A-2 Receiver Performance Parameter Receive Gain Absolute Accuracy Receive Gain Variation with Frequency Receive Noise Psofometric Weighted Signal to Total Distortion Total Gain Half Channel Sine Method Input Level (without transformer distortion) Signal to ...

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... Physical Dimensions inches (millimeters) Order Number NS32FX200VF NS32FX100VF or NS32FV100FV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or ...