IDT75K72100S66BL IDT, Integrated Device Technology Inc, IDT75K72100S66BL Datasheet - Page 2

• Manufacturer Part Number: IDT75K72100S66BL
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT75K72100S66BL

• Lead Free Status / Rohs Status: Not Compliant

Data and Mask Array
ated Mask cell entries as shown in Fig. 1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
IP Co-Processor 256K x 72 Entries
Bus Interface
Bus and the NSE Response Bus.
Request Data Bus. The Command Bus handles the instruction to the NSE
while the Request Data Bus is the main data path to the NSE.
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
tional Index Bus which drives the result of the lookup (or index) to either
an SRAM device or an ASIC. In addition to driving the Index, the NSE
Response Bus also drives the associated SRAM control signals (CE/OE,
and WE) for either ZBT™ or Synchronous Pipeline Burst SRAM devices.
Command Bus
include:
entry, or register.
Features
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Functional Highlights
The NSE has Data cell entries and associ-
The Command Bus loads the specific instructions into the NSE. These
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A Read or Write instruction operates on a specified data entry, mask
Full Ternary 256K x 72 bit content addressable memory
250M sustained lookups per second at 72 and 144 width lookups
Simultaneous Multi Database Lookup (SMDL)
Compatible to lower density ternary NSEs
Advanced Power Management
Dynamic multi database support
Increased Global Mask Registers implementation
Segments individually configurable
36/72/144/288/576 multiple width lookups
Enhanced Multi-match features
Learn new entries with NFA Register per database
Dual bus interface
Cascadable to 8 devices with no glue logic or latency penalty
Glueless interface to standard ZBT™ or
Synchronous Pipelined Burst SRAMs
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
1.2V core power supply
2.5V LVTTL I/O supply
The NSE utilizes a dual bus interface consisting of the NSE Request
The NSE Request Bus is comprised of the Command Bus and the
The 72 bit bi-directional Request Data Bus functions as a multiplexed
The NSE Response Bus is comprised of an independent unidirec-
Read or Write
Figure 1.1
Mask
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SRAM Interface
glueless SRAM interface. The NSE provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and from the SRAM.
Registers
segmentation of the entries, timing of outputs and the SRAM interface,
instructions by masking individual bits during a search.
search from a Lookup operation.
Width Segmentation Capability
structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has
can be configured to meet various system requirements.
Multi Match
has resulted. The result of the lookup, which defines the highest priority
match, is sent along with the Multi-Match signal.
Power Savings and Classification Features
can be pipelined within a series of operations and does not require the user
to wait for the Read to complete before loading the next instruction.
simultaneous writes to a Data entry and a respective external SRAM
location.
A 36-bit lookup can be accomplished by using two Global Mask Registers.
provides a mechanism for the user to write a lookup entry into an unused
location in the NSE and the associated data in external SRAM. This allows
the user to update an entry into the NSE which had not previously been
stored. The Learn writes the new entry, making it available for future
lookups.
The NSEs are capable of performing lookups for comparisons on data
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An SRAM No Wait Read is a Read instruction to an external SRAM that
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In addition to individual writes, the NSE has the ability to perform
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A lookup can be requested in 72-bit, 144-bit, 288-bit or 576-bit widths.
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The NSE implements a fully autonomous Learn Instruction, which
The NSE provides all required address and control signals for a
There are four basic types of registers supported:
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The Multi-Match feature signals to the user that more than one match
See full IDT75K72100 Datasheet for more information.
Dual Write
SRAM No Wait Read
Lookup
Learn
Configuration Registers are used at initialization to define the
Comparand Registers assist in the Learn Instruction.
Result Registers are used to store the resulting index of a
Single Width Array
Multiple Width Arrays within a Single Device
Global Mask Registers are provided to support Lookup
Datasheet Brief 75K72100