AK4125VFP-E2 AKM Semiconductor Inc, AK4125VFP-E2 Datasheet - Page 18

• Manufacturer Part Number: AK4125VFP-E2
• Description: IC SAMPLE RATE CONVERTER 30VSOP
• Manufacturer: AKM Semiconductor Inc
• Series: -r
• Type: Sample Rate Converterr

Specifications of AK4125VFP-E2

• Applications: Automotive Systems, Home Theater, TV
• Mounting Type: Surface Mount
• Package / Case: 30-LSSOP (0.220", 5.60mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 974-1042-2

■
The AK4125 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is
output within 100ms.
■
The change of the clock supplied to AK4125 is shown in
■
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0379-E-05
Internal Reset Function for Clock Change
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN
Note 2. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” for 1024/fso+100ms or more
Note 3. When the PDN pin is not used for this clock change, a distorted signal may output for about 10ms ~ 100ms
UNLOCK pin
Sequence of Changing Clocks
pin changes to “L”. It makes the data on SDTO remain as “0”. SMUTE can also remove this clicking noise.
(typ) after changing clocks.
from the timing PDN pin changes to “H” while the SMUTE pin = “H”.
External clocks
(Input port
PDN pin
(Internal state)
SDTO
SMUTE
(recommended)
Att.Level
or Output port)
-
0dB
∞
dB
Normal operation
Normal data
Clocks 1
Figure 13. Sequence of Changing Clocks
1024/fso
Power-down
Don’t care
Note1
- 18 -
Figure
13.
PLL lock &
fs detection
< 100ms
Note2
Clocks 2
1024/fso
Normal operation
Normal data
[AK4125]
2010/05