SAF-XC164CS-16F40FBB Infineon Technologies, SAF-XC164CS-16F40FBB Datasheet - Page 34

• Manufacturer Part Number: SAF-XC164CS-16F40FBB
• Manufacturer: Infineon Technologies

3.7
The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one independent 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions (deadtime control). The
compare channel can generate a single PWM output signal and is further used to
modulate the capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registers
upon a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled system clock.
Figure 6
For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer T12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).
Data Sheet
f
f
CPU
CPU
The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
The Capture/Compare Unit (CAPCOM6)
CAPCOM6 Block Diagram
Period Register
Period Register
Control Register
Offset Register
Timer T12
Timer T13
Compare
Compare
T12P
T13P
CTCON
T12OF
16-bit
10-bit
Select Register
Compare Register
CC6MSEL
CC Channel 0
CC Channel 1
CC Channel 2
Mode
CMP13
CC60
CC61
CC62
32
Trap Register
CC6MCON.H
Commutation
Control
Control
Logic
Block
Port
Functional Description
CC6POS0
CC6POS1
CC6POS2
CTRAP
CC60
COUT60
CC61
COUT61
CC62
COUT62
COUT63
Derivatives
V2.3, 2006-08
MCB04109
XC164CS