NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 65

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NUC140LD2CN

Manufacturer Part Number
NUC140LD2CN
Description
IC MCU 32BIT 64KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC140LD2CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Power-On-Reset Control Register (PORCR)
Register
PORCR
Bits
[31:16]
[15:0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Descriptions
Reserved
POR_DIS_CODE
Offset
GCR_BA+0x24
30
22
14
6
R/W
R/W
Reserved
The register is used for the Power-On-Reset enable control (write-protection bits)
When power on, the POR circuit generates a reset signal to reset the whole chip
function, but noise on the power may cause the POR active again. User can disable
internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5
to this field.
The POR function will be active again when this field is set to another value or chip is
reset by other reset source, including:
/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip
reset function
This bit is the protected bit. It means programming this needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100.
29
21
13
5
Description
Power-On-Reset Controller Register
POR_DIS_CODE[15:8]
POR_DIS_CODE[7:0]
28
20
12
4
- 65 -
Reserved
Reserved
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
25
17
9
1
Revision V2.01
Reset Value
0x0000_00XX
24
16
8
0

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