XC3195A-3PQ208C Xilinx Inc, XC3195A-3PQ208C Datasheet - Page 25

• Manufacturer Part Number: XC3195A-3PQ208C
• Description: FPGA XC3100A Family 7.5K Gates 484 Cells 270MHz CMOS Technology 5V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3195A-3PQ208C

• Package: 208PQFP
• Family Name: XC3100A
• Device Logic Units: 484
• Device System Gates: 7500
• Number Of Registers: 1320
• Maximum Internal Frequency: 270 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 176
• Ram Bits: 94944
• Re-programmability Support: Yes
• Case: QFP208
• Dc: 97+

Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
November 9, 1998 (Version 3.1)
Figure 25: Master Parallel Mode Circuit Diagram
*
5-k Resistor is
Series With M1
If Readback is
Activated, a
Required in
System Reset
Reprogram
5 k
General-
Purpose
User I/O
+5 V
Pins
R
RESET
M2
HDC
RCLK
D7
D6
D5
D4
D3
D2
D1
D0
Other
I/O Pins
M0 M1PWRDWN
*
Master
FPGA
+5 V
DOUT
CCLK
INIT
A15
A14
A13
A12
A11
A10
D/P
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
N.C.
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
EPROM
8
D7
D6
D5
D4
D3
D2
D1
D0
Collector
XC3000 Series Field Programmable Gate Arrays
Open
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
+5 V
D/P
CCLK
DIN
RESET
M0 M1PWRDWN
*
Slave #1
FPGA
I/O Pins
Other
DOUT
HDC
LDC
INIT
M2
5 k
General-
Purpose
User I/O
Pins
...
+5 V
CCLK
DIN
D/P
Reset
M0 M1PWRDWN
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
*
Slave #n
5 k Each
FPGA
+5 V
I/O Pins
Other
DOUT
HDC
LDC
INIT
M2
5 k
General-
Purpose
User I/O
Pins
X5990
7-27
7