XC3S100E-5TQ144C Xilinx Inc, XC3S100E-5TQ144C Datasheet - Page 74

• Manufacturer Part Number: XC3S100E-5TQ144C
• Description: FPGA Spartan®-3E Family 100K Gates 2160 Cells 657MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S100E-5TQ144C

• Package: 144TQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 2160
• Device Logic Units: 240
• Device System Gates: 100000
• Number Of Registers: 1920
• Maximum Internal Frequency: 657 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 108
• Ram Bits: 73728
• Re-programmability Support: Yes

Functional Description
Voltage Compatibility
The PROM’s V
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
Flash PROM’s V
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
V
XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for
additional information.
Supported Platform Flash PROMs
Table 51
PROM to program one Spartan-3E FPGA. A multiple-FPGA
daisy-chain application requires a
large enough to contain the sum of the various FPGA file
sizes.
Table 51: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
74
V
CCAUX
XC3S1200E
XC3S1600E
Spartan-3E
XC3S100E
XC3S250E
XC3S500E
The FPGA’s VCCO_2 supply input and the Platform
FPGA
supply, nominally 2.5V. See application note
shows the smallest available Platform Flash
CCINT
CCO
Configuration
Number of
1,353,728
2,270,208
3,841,184
5,969,696
supply input must be the same volt-
supply must be either 3.3V for the
581,344
Bits
Platform Flash PROM
Smallest Available
Platform Flash
or 2 x XCF04S
XCF01S
XCF02S
XCF04S
XCF04S
XCF08P
www.xilinx.com
The XC3S1600E requires an 8 Mbit PROM. Two solutions
are possible: either a single 8 Mbit XCF08P parallel/serial
PROM or two 4 Mbit XCF04S serial PROMs cascaded. The
two XCF04S PROMs use a 3.3V V
XCF08P requires a 1.8V V
not already have a 1.8V supply available, the two cascaded
XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator gener-
ates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 52: Maximum ConfigRate Settings for Platform
Flash
Platform Flash
Part Number
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
bitstream generator option.
3.3V, 2.5V, or 1.8V
(VCCO_2, V
3.3V or 2.5V
I/O Voltage
CCINT
1.8V
DS312-2 (v3.8) August 26, 2009
supply. If the board does
CCO
CCINT
)
Product Specification
Table 52
supply while the
ConfigRate
Maximum
Setting
25
12
25
shows the
R