DS90CF384MTDX National Semiconductor, DS90CF384MTDX Datasheet - Page 5

• Manufacturer Part Number: DS90CF384MTDX
• Description: LVDS Flat Panel Display 0.45V 56-Pin TSSOP T/R
• Manufacturer: National Semiconductor

Specifications of DS90CF384MTDX

• Package: 56TSSOP
• Number Of Drivers: 28
• Transmission Data Rate: 1800 Mbps
• Differential Input Low Threshold Voltage: -0.1 V
• Differential Input High Threshold Voltage: 0.1 V
• Typical Operating Supply Voltage: 3.3 V

TPLLS
TPDD
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Symbol
Symbol
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
Transmitter Phase Lock Loop Set (Figure 11 )
Transmitter Power Down Delay (Figure 15 )
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 18 )
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 19 )
RxCLK OUT Period (Figure 8)
RxCLK OUT High Time (Figure 8 )
RxCLK OUT Low Time (Figure 8)
RxOUT Setup to RxCLK OUT (Figure 8 )
RxOUT Hold to RxCLK OUT (Figure 8 )
RxCLK IN to RxCLK OUT Delay 25˚C, V
Receiver Phase Lock Loop Set (Figure 12 )
Receiver Power Down Delay (Figure 16 )
FIGURE 1. “Worst Case” Test Pattern
Parameter
Parameter
CC
= 3.3V (Figure 10 )
5
(Continued)
f = 65 MHz
f = 65 MHz
f = 65 MHz
11.7
13.9
3.45
Min
Min
400
0.7
2.9
5.1
7.3
9.5
7.3
2.5
2.5
5.0
15
12.1
14.3
Typ
Typ
2.2
2.2
1.1
3.3
5.5
7.7
9.9
8.6
4.9
6.9
5.7
7.1
T
DS012887-3
www.national.com
Max
Max
10.2
12.4
14.6
100
5.0
5.0
1.4
3.6
5.8
8.0
9.0
10
50
10
1
Units
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns