STAC9200X5NAEB1XR Integrated Device Technology (Idt), STAC9200X5NAEB1XR Datasheet - Page 34

• Manufacturer Part Number: STAC9200X5NAEB1XR
• Description: Audio Codec 2ADC / 2DAC 24-Bit 32-Pin VFQFPN EP T/R
• Manufacturer: Integrated Device Technology (Idt)
• Type: General Purposer

Specifications of STAC9200X5NAEB1XR

• Package: 32VFQFPN EP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /2 DAC
• Sampling Rate: 192 KSPS
• Number Of Dacs: 2
• Operating Supply Voltage: 3.3 V

IDT™
STAC9200
2-CHANNEL HIGH DEFINITION AUDIO CODEC
2-CHANNEL HIGH DEFINITION AUDIO CODEC
5.4.13. AFG GPIOEn
[31.:4]
Bit
Bit
[1]
[0]
[3]
[2]
[1]
[0]
Set1
Get
Bitfield Name
Bitfield Name
Mask3
Mask2
Mask1
Mask0
Data1
Data0
Rsvd
Table 35. AFG GPIOEn Command Response Format
Table 33. AFG GPIO Command Response Format
Table 34. AFG GPIOEn Command Verb Format
Verb ID
F16
716
IDT CONFIDENTIAL
RW
RW
RW
RW
RW
RW
RW
RW
R
34
Reset
Reset
See bits [7:0] of bitfield table
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Payload
Data for GPIO1 (Pin 34). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it
can be cleared by writing zero (one) here when
the corresponding Polarity Control bit is zero
(one).
Data for GPIO0 (Pin 33). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it
can be cleared by writing zero (one) here when
the corresponding Polarity Control bit is zero
(one).
Reserved
Enable for GPIO3:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
Enable for GPIO2:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
Enable for GPIO1:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
Enable for GPIO0:
0= pin is disabled (Hi-Z state);
1= pin is enabled; behavior determined by
GPIO Direction control
00
STAC9200
Description
Description
See bitfield table
0000_0000h
Response
PC AUDIO
V 1.6 01/08