GS84036AT-150 GSI TECHNOLOGY, GS84036AT-150 Datasheet - Page 23

• Manufacturer Part Number: GS84036AT-150
• Description: SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 10ns/3.8ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS84036AT-150

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 4
• Number Of Words: 128K

Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.19a 2/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSC
ADSP
CK
ZZ
Setup
Hold
tKC
tKC
tKH
tKH
Sleep Mode Timing Diagram
tKL
tKL
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tZZS
tZZH
GS84018/32/36AT/B-180/166/150/100
tZZR
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