APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 29

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

PLL I/O Constraints
PLL locking is guaranteed only when the following constraints are followed:
Table 2-10 • PLL I/O Constraints
I/O Type
SSO
PLL locking is guaranteed only when using low drive strength and
low slew rate I/O. PLL locking may be inconsistent when using high
drive strength or high slew rate I/Os
APA300
APA600
APA1000
APA300
APA600
APA1000
T
J
≤
v5.9
–40°C
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
≤
≤
≤
≤
≤
≤
16 SSO
32 SSO
32 SSO
20 SSO
64 SSO
64 SSO
≤
≤
≤
≤
≤
≤
8 SSO
16 SSO
16 SSO
12 SSO
32 SSO
32 SSO
ProASIC
With FIN
outputs
simultaneously
With FIN
outputs switching on positive
clock edge, half switching on
the negative clock edge no less
than 10 ns later
PLUS
Value T
No Constraints
≤
Flash Family FPGAs
≤
50 MHz and half
J
180 MHz and
> –40°C
switching
2-19