CS4299-JQ Cirrus Logic Inc, CS4299-JQ Datasheet - Page 10

• Manufacturer Part Number: CS4299-JQ
• Description: Audio Codec 1ADC / 1DAC 18-Bit/20-Bit 48-Pin LQFP
• Manufacturer: Cirrus Logic Inc
• Type: PCMr

Specifications of CS4299-JQ

• Package: 48LQFP
• Adc/dac Resolution: 18/20 Bit
• Number Of Channels: 1ADC /1 DAC
• Sampling Rate: 48 KSPS
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Number Of Dacs: 1
• Operating Supply Voltage: 3.3|5 V

2. GENERAL DESCRIPTION
The CS4299 is a mixed-signal serial audio Codec
compliant to the Intel
tion, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com-
munications between the CS4299 and the remain-
der of the system. The CS4299 contains two
distinct functional sections: digital and analog. The
digital section includes the AC-link interface,
S/PDIF interface, serial data port, Sample Rate
Converters, and power management support. The
analog section includes the analog input multiplex-
er (mux), stereo output mixer, mono output mixer,
stereo Analog-to-Digital Converters (ADCs), ste-
reo Digital-to-Analog Converters (DACs), and
their associated volume controls.
2.1
All communication with the CS4299 is established
with a 5-wire digital interface to the controller, as
shown in Figure 7. This interface is called the
AC-link. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co-
10
10
AC-Link
®
Audio Codec ‘97 Specifica-
Digital AC’97
Controller
Figure 7. AC-link Connections
SDATA_OUT
SDATA_IN
BIT_CLK
RESET#
SYNC
decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form-
ing 13 groups referred to as ‘slots’. During each au-
dio frame, data is passed bi-directionally between
the CS4299 and the controller. The input frame is
driven from the CS4299 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re-
sponsible for issuing reset commands via the RE-
SET# signal. Following a Cold Reset, the CS4299
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4299 AC-link signals must use
the same digital supply voltage as the controller
chip, either +5 V or +3.3 V. See Section 3, AC Link
Frame Definition, for detailed AC-link informa-
tion.
2.2
The CS4299 contains a set of AC ’97 compliant
control registers and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4299. Read access-
es of the control registers by the AC ’97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in its
Control registers
CODEC
CS4299
CS4299
DS319PP6