HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 39

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

POSITION
POSITION
POSITION
31-24
23-18
17-14
13-9
13-9
BIT
8-5
4-0
BIT
8-5
4-0
BIT
N/A
Not Used
Reserved
Symbol Tracking Lead Gain Mantissa
(Track)
Symbol Tracking Lead Gain Exponent
(Track)
Symbol Tracking Lag Gain Mantissa
(Track)
Symbol Tracking Lag Gain Exponent
(Track)
TABLE 34. SYMBOL TRACKING LOOP FILTER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER
Symbol Tracking
Lead Gain Exponent
(Acquisition)
Symbol Tracking Lag
Gain Mantissa
(Acquisition)
Symbol Tracking Lag
Gain Exponent
(Acquisition)
Symbol Tracking Loop
Filter Lag Accumulator
Initialization
FUNCTION
TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued)
FUNCTION
TABLE 33. SYMBOL TRACKING LOOP FILTER GAIN (TRK) CONTROL REGISTER
FUNCTION
39
These bits set the lead gain exponent as given by:
Symbol Tracking Lead Gain Exponent = 2
where E corresponds to the 5-bit binary value programmed here. Thus, a gain range from
2
Binary. Bit position 13 is the MSB.
Format same as lead gain mantissa. Bit position 8 is the MSB.
Format same as lead gain exponent. Bit position 4 is the MSB.
-1
Writing to this address initializes the lag accumulator with the contents of the four Microprocessor
Interface Holding Registers at the start of the next loop filter computation cycle. The contents of the
holding registers should not be changed until after the start of a new compute cycle since the current
contents of the holding registers are loaded at the compute cycle start. At a slow rate, it could take 1 low
rate symbol time to change. The Microprocessor Interface should be used to read an internal status
register which signals when the lag accumulator load is complete (see Table 13 in the “Microprocessor
Interface” on page 27). The contents of the holding registers are loaded into the 32 MSBs of the lag
accumulator and the 8 LSBs are zeroed.
It is a good practice to load the LAG accumulators at the very end of a configuration load sequence.
to 2
-32
relative to the MSB position of the NCO control word may be achieved for E = 11111 to 00000
DESTINATION ADDRESS = 17
DESTINATION ADDRESS = 18
DESTINATION ADDRESS = 19
No programming required.
Reserved. Set to 0 for proper operation.
Format same as lead gain mantissa (see Table 32). Bit position 17 is the MSB.
Format same as lead gain exponent (see Table 32). Bit position 13 is the MSB.
Format same as lead gain mantissa (see Table 32). Bit position 8 is the MSB.
Format same as lead gain exponent (see Table 32). Bit position 4 is the MSB.
HSP50210
-(32-E),
DESCRIPTION
DESCRIPTION
DESCRIPTION
July 2, 2008
FN3652.5