SST49LF080A-33-4C-NH Microchip Technology, SST49LF080A-33-4C-NH Datasheet - Page 15

• Manufacturer Part Number: SST49LF080A-33-4C-NH
• Description: Flash 1M X 8 33MHz
• Manufacturer: Microchip Technology

Specifications of SST49LF080A-33-4C-NH

• Data Bus Width: 8 bit
• Memory Type: NAND
• Memory Size: 8 Mbit
• Architecture: Sectored
• Interface Type: LPC
• Access Time: 33 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 1024 KB x 8
• Lead Free Status / Rohs Status: No RoHS Version Available

8 Mbit LPC Flash
SST49LF080A
Multiple Device Selection
Multiple LPC flash devices may be strapped to increase
memory densities in a system. The four ID pins, ID[3:0],
allow up to 16 devices to be attached to the same bus by
using different ID strapping in a system. BIOS support, bus
loading, or the attaching bridge may limit this number. The
boot device must have an ID of 0 (determined by ID[3:0]);
subsequent devices use incremental numbering. Equal
density must be used with multiple devices.
When used as a boot device, ID[3:0] must be strapped as
0000; all subsequent devices should use a sequential up-
count strapping (i.e. 0001, 0010, 0011, etc.). With the hard-
ware strapping, ID information is included in every LPC
address memory cycle. The ID bits in the address field are
inverse of the hardware strapping. The address bits
[A
IDs. See Table 7 for IDs. The SST49LF080A will compare
these bits with ID[3:0]’s strapping values. If there is a mis-
match, the device will ignore the remainder of the cycle.
TABLE 7: Multiple Device Selection
©2006 Silicon Storage Technology, Inc.
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
24
:A
Device #
23
, A
21
:A
Configuration
20
] are used to select the device with proper
Strapping
Hardware
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address Bits Decoding
A
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
24
A
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
23
A
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
21
T7.0 1235
A
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
20
15
Registers
There are two registers available on the SST49LF080A,
the General Purpose Inputs Registers (GPI_REG) and the
JEDEC ID Registers. Since multiple LPC memory devices
may be used to increase memory densities, these registers
appear at its respective address location in the 4 GByte
system memory map. Unused register locations will read
as 00H. Any attempt to read registers during internal Write
operation will respond as “Write operation status detection”
(Data# Polling or Toggle Bit). Any attempt to write any reg-
isters during internal Write operation will be ignored. Table
9 lists GPI_REG and JEDEC ID address locations for
SST49LF080A with its respective device strapping.
TABLE 8: General Purpose Inputs Register
Bit
7:5
4
3
2
1
0
Function
Reserved
GPI[4]
Reads status of general
purpose input pin
GPI[3]
Reads status of general
purpose input pin
GPI[2]
Reads status of general
purpose input pin
GPI[1]
Reads status of general
purpose input pin
GPI[0]
Reads status of general
purpose input pin
32-PLCC
30
3
4
5
6
-
S71235-02-000
Pin #
Data Sheet
32-TSOP
11
12
13
14
T8.0 1235
6
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