TEF6862HL/V1.557 NXP Semiconductors, TEF6862HL/V1.557 Datasheet - Page 19

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TEF6862HL/V1.557

Manufacturer Part Number
TEF6862HL/V1.557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TEF6862HL/V1.557

Lead Free Status / Rohs Status
Compliant
Philips Semiconductors
TEF6862_1
Product data sheet
8.2.1 Mode and subaddress byte for write
Table 20.
Table 21.
Bit
7 to 5
4
3 to 0
Fig 9. Write to CONTROL register with swap, REGC = 1
MODE2
7
BUFFER
CONTROL
MODE[2:0]
SA[3:0]
Symbol
REGC
MSA - mode and subaddress byte bit allocation
MSA - mode and subaddress byte bit description
MODE1
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
6
Rev. 01 — 14 September 2006
address
previous
previous
previous
previous
previous
previous
MODE0
Description
mode; see
register mode
subaddress; write data byte subaddress 0 to 15. The subaddress
value is auto-incremented and will revert from SA = 15 to SA = 0. The
auto-increment function cannot be switched off.
5
0 = buffer mode or back mode: previous tuning data is default for
new I
before I
1 = control mode or current mode: current tuning data is default for
new I
register data before I
MODE = load
REGC = 1
SA = 3
MSA
2
2
C-bus write (data of the BUFFER register is not changed
C-bus write (the BUFFER register is loaded with CONTROL
current
current
current
current
current
current
2
C-bus write); see
Table 22
REGC
current
current
current
current
current
current
byte 3
load
4
Car Radio Enhanced Selectivity Tuner (CREST)
new
byte 4
2
C-bus write); see
SA3
3
Figure 8
new
byte 5
swap
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
new
SA2
P
2
Figure 9
SA1
TEF6862
1
001aab789
current
current
current
current
current
current
current
current
current
new
new
new
SA0
19 of 65
0

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