LMX9820SB/NOPB National Semiconductor, LMX9820SB/NOPB Datasheet - Page 32

• Manufacturer Part Number: LMX9820SB/NOPB
• Manufacturer: National Semiconductor

Specifications of LMX9820SB/NOPB

• Lead Free Status / Rohs Status: Compliant

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14.0 Application Information
Figure 21 on page 32 represents a typical system sche-
matic for the LMX9820.
14.1 MATCHING NETWORK
The antenna matching network may or may not be
required, depending upon the impedance of the antenna
chosen. A 6.8pF blocking capacitor is recommended.
14.2 FILTERED POWER SUPPLY
It is imperative that the LMX9820 be provided with ade-
quate Ground planes and a filtered power supply. It is
highly recommended that a 0.1 µF and a 10 pF bypass
capacitor be placed as close as possible to VCC (pad H2)
on the LMX9820.
14.3 HOST INTERFACE
To set the logic thresholds of the LMX9820 to match the
host system, IOVCC (pad H12) must be connected to the
logic power supply of the host system. It is highly recom-
mended that a 10 pF bypass capacitor be placed as close
as possible to the IOVCC pad on the LMX9820.
Notes:
Capacitor values, C1, C2, C31 & C32, may vary depending on board design crystal manufacturer specification.
Single ground plane is used for both RF and Digital grounds.
10 pF
C1
B1 Antenna
10 pF
Figure 21. Example System Schematic with pre-selected 115.2kbit/s UART speed
12 MHz
Y1
0.01 µF
10 pF
6.8 pF
C2
H8
B9
B8
H2
RF_inout
Clk+
Clk-
VCC
RF GND
H12
IOVCC
D12, G11
Dig_gnd[1:2]
10 pF
32
LMX9820
0.01 µF
USBGND
G12
ISEL2 (pad H13) and ISEL1 (pad J13) can be strapped to
the host logic 0 and 1 levels to set the host interface boot-
up configuration. Alternatively both ISEL2 and ISEL1 can
be hardwired over 10K
Env0 (pad E9) and Env1 (pad B11) can be left uncon-
nected (both are read as high) if no ISP capability is
required. If the environment mode ISP needs to be acti-
vated by hardware (alternatively a firmware upgrade com-
mand can be used) then Env0 must be set to Logical Low
and Reset needs to be set. Upon removal of Reset, the
LMX9820 boots into the mode corresponding to the values
present on Env0 and Env1.
14.4 CLOCK INPUT
The clock source must be placed as close as possible to
the LMX9820. The quality of the radio performance is
directly related to the quality of the clock source connected
to the oscillator port on the LMX9820. Careful attention
must be paid to the crystal/oscillator parameters or radio
performance could be drastically reduced.
14.5 SCHEMATIC AND LAYOUT EXAMPLES
Reset_5100
Uart_cts
Reset_b
Uart_rts
Uart_rx
Uart_tx
ISEL1
ISEL2
Env0
Env1
pull-up/pull-down resistors.
J13
H13
C8
D9
D10
C10
D11
G8
E9
B11
Connect
system
UART bus.
Reference
Table 24 on
page 20 for
correct POR
timing.
Reference
Table 18 on
page 15.
Reference
Table 19 on
page 15.
to