S4804CBI41 Applied Micro Circuits Corporation, S4804CBI41 Datasheet - Page 2

• Manufacturer Part Number: S4804CBI41
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S4804CBI41

• Lead Free Status / Rohs Status: Not Compliant

Line Side
Interface
SONET
S4804CBI41: RHINE
STS-48 POS/ATM SONET MAPPER
Overview and Applications
Sonet/SDH Processing
The S4804 implements SONET/SDH processing and full-
duplex ATM/packet-mapping functions for STS-48/STM-16,
STS-12/STM-4, or STS-3/STM-1 data streams. It can support
either a single STS-48c/AU-4-16c or any valid combination of
STS-12c/AU-4-4c or STS-3c/AU-4 signals within an STS-48/
STM-16. The S4804 also supports 4 STS-12/STM-4 signals
(each containing a single STS-12c/AU-4-4c or 4 STS-3c/AU-
4), or 16 STS-3c/STM-1 signals each containing an STS-3c/
AU-4.
A TOH/SOH interface provides direct add/drop capability for
E1, E2, F1, and both Section and Line DCC channels. The
S4804 also includes a clear channel mode that enables the
direct transmission of system payload from the system inter-
face to the line-side interface.
On the transmit side, the S4804 generates section, line, and
path overhead. It performs framing pattern insertion (A1, A2),
scrambling, alarm-signal insertion, and generates section,
line, and path Bit Interleaved Parity (B1/B2/B3) for far-end
performance monitoring.
On the receive side, the S4804 processes section, line, and
path overhead. It performs framing (A1, A2), descrambling,
alarm detection, pointer processing, Bit Interleaved Parity
monitoring (B1/B2/B3), and error-count accumulation for
performance monitoring.
ATM Processing
When configured for ATM cell processing, the S4804’s trans-
mit ATM processor(s) will perform all necessary cell process-
ing as defined by ATM UNI3.1, ITU-T I.432.1, and I.432.2.
TYPICAL APPLICATIONS: S4804CBI - RHINE in ATM or POS System
Single STS-48 / Quad STS-12/ 16xSTS-3
POS or ATM over SONET Application
Single OC-48
Four OC-12
Sixteen OC-3
Either
or
or
Transceiver
HP / Lucent
Fiber Optic
200 Minuteman Road, Andover, MA 01810 Ph: [phone] Fax: [phone]
SerTxD±
SerRxD±
AMCC 3055
For OC-48 Mode:
SONET XCVR
Clk Recovery
Reference
P/S & S/P
Clock
with
TX_SONETCLK_IN
RX_SONETCLK[2]
RX_LOSEXT[1]
RX_DATA[15:0]
TX_DATA[15:0]
Control
AMCC
Microprocessor
TOH Insertion
and Extraction
S4804CBI
Addr
AMCC
RHINE
HDLC Processing
When configured for POS mode, the S4804’s HDLC proces-
sor(s) provides HDLC packet processing as defined by IETF
RFCs 1619, 1662 and 2615. In addition, the S4804 optionally
performs scrambling (X
Direct Map Mode
Direct Map Mode allows to map any protocol directly into the
Sonet/SDH Synchronous Payload Envelope, by-passing the
ATM and HDLC processing circuitry.
Automatic Protection Switching
The S4804 provides APS input and output interfaces to
convey signals between two S4804 devices configured for
APS operation. This configuration supports both 1+1 and 1:1
configurations.
Line-side Interface
On the line side, the S4804 supports a 16-bit parallel
interface, operating at 155MHz for a single OC-48 optical
interface. It provides serial interfaces at either 622 MHz or
155 MHz for OC-12 and/or OC-3 optical interfaces. Mixed
OC-3 / OC-12 line rates are supported.
System Interface
The S4804 supports a 32-bit, 100-MHz system interface. For
ATM cell transfers, the S4804 supports Utopia Level 3
interface. For packet transfers, the S4804 supports
FlexBus
quad, 8-bit extension of the Utopia 3.
Control
14
Data
TM
16
interface. The S4804 also provides support for a
TX_CLK
TX_SYS_DAT[31:0]
RX_SYS_DAT[31:0]
RX_CLK
Product Brief Version 2.0 - January 2002
43
+1).
PRODUCT BRIEF
Multi
Channel
Link Layer
Device
IP Router or ATM Switch
Switching/
Routing
Logic