AD6650BBC Analog Devices Inc, AD6650BBC Datasheet - Page 30

• Manufacturer Part Number: AD6650BBC
• Manufacturer: Analog Devices Inc

Specifications of AD6650BBC

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Lead Free Status / Rohs Status: Not Compliant

AD6650
MICROPORT CONTROL
The AD6650 has an 8-bit microprocessor port. The microport
interface is a multimode interface that allows flexibility when
dealing with the host processor.
There are two modes of bus operation: Intel® nonmultiplexed
mode (INM) and Motorola nonmultiplexed mode (MNM). The
mode is selected based on the host processor and which mode
is best suited for that processor. The microport has an 8-bit data
bus (D[7:0]), 3-bit address bus (A[2:0]), three control pin lines
( CS , DS or RD , and R/ W or WR ), and one status pin ( DTACK
or RDY). The functionality of the control signals and status line
changes slightly depending on the selected mode. Refer to the
timing diagrams in Figure 10 through Figure 13 and the
descriptions in the Programming Modes, Intel Nonmultiplexed
Mode (INM), and Motorola Nonmultiplexed Mode (MNM)
sections for details on the operation of each mode.
EXTERNAL MEMORY MAP
The external memory map is used to gain access to the channel
address space. The 8-bit data and address buses are used to set
the eight registers shown in Table 13. These registers are
collectively referred to as the external interface registers because
they control all access to the channel address space and global
chip functions. The use of each register is described in Table 13.
Table 13. External Memory Map
Addr.
(Hex)
7
6
5
4
3
2
1
0
Mnemonic
Access Control Register
(ACR)
Channel Address Register
(CAR)
Special Function Register 2
(SF2)
Special Function Register 1
(SF1)
Special Function Register 0
(SF0)
Data Register 2 (DR2)
Data Register 1 (DR1)
Data Register 0 (DR0)
Bit No.
7
6
5 to 2
1 to 0
7 to 0
6
5
4
3 to 1
0
5
4
3 to 1
0
7 to 4
3
2
1
0
7 to 4
3 to 0
15 to 8
7 to 0
Description
Auto-increment
Reserved (write low)
Instruction [3:0]
A[9:8]
A[7:0]
AGC sync enable
DC correction
sync enable
PN sync enable
Reserved
Issue Soft_SYNC
First sync only
Enable edge- sensitivity
Reserved
Enable Pin_SYNC
Reserved
Status of Channel B
Enable Channel B
Status of Channel A
Enable Channel A
Reserved
D[19:16]
D[15:8]
D[7:0]
Rev. A | Page 30 of 44
ACCESS CONTROL REGISTER (ACR)
Bit 7 of the ACR register is the auto-increment bit. If this bit is set to
1, the CAR register, described in the Channel Address Register
(CAR) section, increments in value after every access to the
channel. This allows blocks of address space, such as coefficient
memory, to be initialized more efficiently.
Bit 6 of the ACR register is unused and must be written low.
Bit 5 to Bit 2 of the ACR register are instruction bits that allow
multiple AD6650s to receive the same write access. The instruction
bits allow a single or multiple (up to four) AD6650 chip(s) to be
configured simultaneously. There are seven possible instructions
that are defined in Table 14, where x represents disregarded
values in the digital decoding.
If multiple AD6650 chips are using the same CS line, readback
is not valid because of the potential for bus contention. Therefore,
if device readback capability is desired, the CS lines should be
separated for individual control. To facilitate device debug and
verification, the use of separate CS lines for each AD6650 is
recommended.
Bit 1 to Bit 0 of the ACR register are address bits that decode which
channel is to be accessed. Because the channels of the AD6650
cannot be programmed independently, these bits should be set
to 0.
CHANNEL ADDRESS REGISTER (CAR)
The CAR register represents the 8-bit internal address of each
channel. If the auto-increment bit of the ACR is 1, this value is
incremented after every access to the DR0 register, which in
turn accesses the location pointed to by this address.
SPECIAL FUNCTION REGISTERS
The AD6650 has three special function registers, SF0, SF1, and
SF2, that control synchronizing and enabling of the channels. SF0
controls channel enabling, SF1 controls Pin_SYNC, and SF2
controls Soft_SYNC. For SF0, Bit 0 and Bit 2 allow Channel A
and Channel B, respectively, to exit sleep mode by the method
selected in SF1. Bit 1 and Bit 3 are read-only bits and indicate
whether Channel A and Channel B, respectively, are active. A 1
indicates that the channel is active, and a 0 indicates that it is
not active. Bits 4 through Bit 7 are unused.
For SF1, if Bit 0 is set to 1, both channels wait for a pulse to
appear on the SYNC pin before exiting sleep mode; otherwise,
the channels assume a soft start is desired and wait for the start
holdoff counter to issue a sync. When Bit 5 is set, both channels
ignore all subsequent attempts to resync once they have exited
sleep mode.