CY7C68300A-56LFXC Cypress Semiconductor Corp, CY7C68300A-56LFXC Datasheet - Page 5

• Manufacturer Part Number: CY7C68300A-56LFXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68300A-56LFXC

• Lead Free Status / Rohs Status: Compliant

Pin Descriptions
3.2
3.2.1
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB.
3.2.2
The clock and data pins for the I
connected to your configuration EEPROM and to V
2.2k resistors.
3.2.3
The CY7C68300A requires a 24-MHz signal to derive internal
timing. Typically a 24-MHz parallel-resonant fundamental
mode crystal is used, but a 24-MHz square wave from another
source can also be used. If a crystal is used, connect the pins
to XTALIN and XTALOUT, and also through 20-pF capacitors
to GND. If an alternate clock source is used, apply it to XTALIN
and leave XTALOUT open.
3.2.4
ATA_EN allows bus sharing with other host devices. Setting
ATA_EN = 1 enables the ATA interface for normal operation.
Setting ATA_EN = 0 disables (High-Z) the ATA interface pins
and removes the CY7C68300A from the USB. Because the
CY7C68300A supports a true low-power USB suspend state,
new functionality was added to ensure that transitions of the
Note:
Document #: 38-08031 Rev. *E
SSOP
2.
Pin
46
47
48
49
50
51
52
53
54
55
56
A # sign after the signal name indicates that it is an active LOW signal.
QFN
Pin
Additional Pin Descriptions
DPLUS, DMINUS
SCL, SDA
XTALIN, XTALOUT
ATA_EN
39
40
41
42
43
44
45
46
47
48
49
VBUS_PW
Pin Name
ARESET#
R_VALID
RESET#
ATA_EN
DD10
DD12
DD11
GND
DD8
DD9
V
CC
(continued)
O/Z
PWR
Type
GND
I/O
I/O
I/O
I/O
I/O
Pin
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
I
I
I
[1]
[1]
[1]
[1]
[1]
[1]
2
C-compatible port should be
Input
Input – If CY7C68300A is not
in mfg mode, polled every 20
ms after start-up. If LOW,
SSOP pins 36–38, 41–45
and 47 or QFN pins 29–31,
34–38 and 40 are three-
stated.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Default State at Start-up
This part is not recommended for new designs
CC
through
Bridge for new designs
VBUS detection. Indicates to the CY7C68300A that VBUS
power is present.
ATA Reset.
Ground.
Active LOW Reset. Resets the entire chip. This pin is normally
tied to VCC through a 100K resistor, and to GND through a
0.1-µF capacitor, supplying a 10-ms reset.
V
Active HIGH. ATA interface enable. Allows ATA bus sharing
with other host devices. Setting ATA_EN = 1 enables the ATA
interface for normal operation. Disabling ATA_EN three-states
(High-Z) the ATA interface and halts the ATA interface state
machine logic.
ATA Data bit 8.
ATA Data bit 9.
ATA Data bit 10.
ATA Data bit 11.
ATA Data bit 12.
ATA_EN signal could be detected properly under all circum-
stances. The CY7C68300A will behave in the following
manner:
CC
20pF
• If ATA_EN transitions to '0' during normal operation, the
• If ATA_EN transitions to '1' when in low-power mode and
• If the CY7C68300A is already in suspend and ATA_EN
• If the CY7C68300A is already in suspend and ATA_EN
CY7C68300A will disconnect from the USB and drop to a
low-power mode.
no other condition is causing the low-power state, the
CY7C68300A will return to a post-reset state and reconnect
to the USB.
transitions to '0', the CY7C68300A will resume only long
enough to stop driving the ATA interface (High-Z) and drop
back to low-power again.
transitions to '1', the CY7C68300A will resume only long
enough to start driving the ATA interface and drop to low-
power again.
. Connect to 3.3V power source.
Figure 3-3. XTALIN, XTALOUT Diagram
Pin Description
24MHz crystal
CY7C68300A
Page 5 of 21
20pF