DT28F160F3T95 Intel, DT28F160F3T95 Datasheet - Page 13

• Manufacturer Part Number: DT28F160F3T95
• Manufacturer: Intel

Specifications of DT28F160F3T95

• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

3.0
3.1
3.1.1
3.1.2
PRELIMINARY
Principles of Operation
The 3 Volt Fast Boot Block Flash memory components include an on-chip Write State Machine
(WSM) to manage block erase and program. It allows for CMOS-level control inputs, fixed power
supplies, and minimal processor overhead with RAM-like interface timings.
Bus Operations
The local CPU reads and writes flash memory in-system. All flash memory read and write cycles
conform to standard microprocessor bus cycles.
Read
The flash memory has three read modes available: read array, identifier codes, and status register.
These modes are accessible independent of the V
Array, Read Identifier Codes, or Read Status Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit from reset, the device defaults to read array
mode.
When reading information from main blocks in read array mode, the device supports two high-
performance read configurations: synchronous burst mode and asynchronous page mode. Page
mode and synchronous burst-mode reads are enabled by writing the Set Read Configuration
Register command to any device address.
Synchronous burst mode is enabled by writing to the read configuration register. This sets the read
configuration, burst order, burst length, and frequency configuration. In synchronous burst mode,
the device latches the initial address then outputs a sequence of data with respect to the input CLK
and read configuration setting. Synchronous burst reads can be terminated after one cycle in main
blocks. Asynchronous page mode is the default state and provides a high data transfer rate for non-
clocked memory subsystems. In this state, data is internally read and stored in a high-speed page
buffer. A
Read operations from the parameter blocks, identifier codes and status register transpire as single-
synchronous or asynchronous read cycles. The read configuration register setting determines
whether or not read operations are synchronous or asynchronous.
For all read operations, CE# must be driven active to enable the devices, ADV# must be driven low
to open the internal address latch, and OE# must be driven low to activate the outputs. In
asynchronous mode, the address is latched when ADV# is driven high. In synchronous mode, the
address is latched by ADV# going high or ADV# low in conjunction with a rising (falling) clock
edge, whichever occurs first. WE# must be at V
different read cycles.
Output Disable
With OE# at a logic-high level (V
placed in a high-impedance state.
1:0
addresses data in the page buffer. The page size is four words.
IH
), the device outputs are disabled. Output pins DQ
IH
PP
.
Figure 14
voltage. The appropriate read command (Read
through
Figure 19
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illustrate the
0
–DQ
15
are
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